Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > Programmable Delay Block

Programmable Delay Block Search results

?
?
total search40 articles
2012-12-07 Synchroniser with programmable MTBF capabilities
Here's a high frequency synchroniser circuit with programmable mean-time-between-failure capabilities well suited for high frequency clock gating and input signal synchronisation applications
2005-08-08 Introduction to Programmable Systems-on-a-Chip
There are a variety of programmable SoCs complete with underlying architectures and technologies. Tradeoffs exist between different programmable SoC devices
2012-02-29 Designing high frequency synchronizer with programmable MTBF features
Read about a high frequency synchronizer circuit with programmable mean-time-between-failure capabilities that is well suited for high frequency clock gating and input signal synchronization applications
2014-04-24 Tips for using PDB in motor control apps on Kinetis
Read about the MPC5777M specific PLL and clock divider settings to achieve 300MHz Core 0 / Core 1 and 200MHz Fast Crossbar (FXBAR) / Core 2 operation.
2004-11-01 Omron PLCs feature MULCE engine
Omron announced the development of new PLCs with a new addition of high-speed function block processing
2008-04-16 Manage circuit board power with PLDs
This article proposes a design solution to the complex power management problem in circuit board design: the use of a programmable, mixed-signal power management device
2005-08-23 LatticeXP FPGAs exhibit sharp drop in standby current
Lattice Semiconductor has added a power-saving feature to its line of LatticeXP family of non-volatile field programmable gate arrays
2003-08-12 Lattice Semi broadens ispXPLD product offerings
Lattice Semiconductor has released two additional members of its in-system programmable eXpanded PLD family - 51024MX and 5256MX
2004-06-01 Embedded synthesis enhances high-density FPGA tools
Tools developed specifically for deep submicron programmable devices are emerging, enabling 100,000 gate and greater FPGAs to become mainstream choices
2002-02-26 Altera PLDs offer three times more memory
Designed using the company's TriMatrix memory structure, the new line of Stratix PLDs from Altera offers up to 10Mb of RAM and 1,650 embedded memory blocksclaimed to be three times more than any other device.
2005-05-12 Maxim IC suits TFT LCD apps
The MAX8758 IC from Maxim includes a high-performance step-up regulator, a high-speed operational amplifier, and a logic-controlled, high-voltage switch-control block with programmable delay.
2007-08-03 Virtex-5 FPGAS are interoperable with 800Mbps DDR3
Xilinx Inc. claims that its Virtex-5 FPGA devices are now interoperable with 800Mbps DDR3 SDRAM devices from leading memory suppliers.
2012-09-07 Implement digital power control using LLC resonant converters
Read about a digital power control implementation using line level control resonant converters based on a flexible 32bit microcontroller.
2006-11-06 Xilinx unveils new design solution for Virtex-5 LXT
Xilinx announced the availability of a complete logic design solution including an update to its ISE design tools for their newest Virtex-5 LXT Platform FPGAs.
2014-07-28 Utilising ARM Cortex-M based SoCs (Part 2)
The second instalment compares the capabilities of a standard microcontroller approach to the design of an embedded application to that of a system on chip approach.
2005-09-01 The basics of implementing DSP functions on low-cost FPGAs
For cutting-edge designs where cycles are tight, requirements are fluid, and expected volumes are uncertain, system companies implement most core functionality and DSP in low-cost FPGAs.
2005-09-22 TD-SCDMA serves as a new battleground for 3G
The technology, which relies on a combination of TDD and synchronous CDMA, offers some key advantages.
2004-03-16 Synthesis methods for ASIC, FPGA designs
Design methodologies that employ cross-implementation EDA technology such as the MultiPoint provide the flexibility to implement a design in the best possible medium.
2005-03-04 ST flash memory chip tailored for 3G mobile phones
ST rolled out a 256Mb NOR flash memory chip that uses a 2bit/cell architecture to provide increased memory density in a small-sized die.
2000-12-01 SoCs likely to pose heading-off test problems
This technology news article describes the problems and solutions test engineers should face when confronting SoC designs.
2007-03-01 RGs to overcome triple-play hurdles
New technology platforms will provide the foundation for new-generation RG solutions that will enable next-generation services along with the flexibility to differentiate offerings with new, advanced features.
2003-12-16 PLLs, DLLs becoming reusable IP
PLLs and DLLs are becoming increasingly important in the SoC design and are gradually turning into IP that can actually be reused by ordinary mortals.
2012-12-12 Perform efficient debug of multi-core MCUs
The real challenge is the processing of the high quantity of debug information coming from all cores and its proper presentation in real-time on the developer's screen.
2012-07-17 Optimizing FPGAs for low power apps
Know the low-power design techniques for the families of 7 series FPGAs.
2014-12-29 Optimise system energy consumption with MRAM
Find out whether the fast-write and power-up-to-write times for MRAM can significantly reduce total system energy consumption compared to either EEPROM or Flash.
2015-06-09 Nothing left to be invented in embedded control (Part 3)
In Part 3, we explore a few more examples of core independent peripherals; combining their functionality with analogue peripherals to create new intelligent analogue solutions.
2015-05-25 Nothing left to be invented in embedded control (Part 2)
In this instalment, we learn that the power of the core independent peripherals is multiplied when we connect them together, relieving the CPU from potentially large computational loads and real-time constraints.
2001-03-01 Logic suppliers seek ways to embed FPGAs
Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility.
2006-04-03 FPGAs consumed by power issues
Power issues charged up the recent FPGA 2006 symposium, and for good reasonmany observers see high power consumption as perhaps the biggest factor limiting wider usage of the devices.
2015-09-22 Examining the most underrated FPGA design tool ever
There is a design tool that is being quietly adopted by FPGA engineers because, in many cases, it produces results that are better than hand-coded counterparts.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top