Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > RISC architecture

RISC architecture Search results

total search306 articles
2004-11-02 ST MCU based on the SmartJ RISC architecture
ST unveiled a new smartcard MCU in its ST22 range based on the SmartJ Java-accelerated RISC architecture.
2013-06-19 Processors feature Imagination's MIPSr5 architecture
The OCTEON III family of 1-48 core processors claim to deliver more than 100Gb/s of application performance per chip, and provide 120GHz of 64bit compute processing per chip.
2011-02-01 Korea's Dongbu chooses EnSilica RISC processor
Dongbu HiTek chose the eSi-1600 after evaluating it against other established embedded RISC processors, and proving that it had 20 percent lower gate count and was 36 percent faster
2004-11-24 Introduction to the MAXQ Architecture
This app note introduces the MAXQ RISC architecture with a variety of complex analog functions.
2007-08-20 8bit flash MCU has advanced RISC architecture
Elan Microelectronics has released the 40MIPS high-speed 8bit flash MCU with advanced RISC architecture.
2008-08-29 Unifying RISC and DSP
The Hyperstone E1-32XSR core represents a unique microprocessor architecture: The combination of a high performance RISC processor with an additional powerful DSP instruction set and on-chip MCU functions.
1999-06-01 Unified RISC/DSPs for multimedia applications and Internet enabling devices
The paper starts with a general overview on features of RISC processors in comparison with DSPs. It continues with a description on methods how to combine RISC and DSP processors, followed by a detailed description of hyperstone's unified RISC/DSP architecture, including system development. in between them.
2005-05-05 Tools suit XAP 32bit RISC core
Cambridge Consultants' new tool set is comprised of the Gnu Compiler Collection C/C++ compiler and the uCLinux and Micrium (C/OS-II real-time operating systems.
2004-05-24 StarCore launches DSP architecture and cores
StarCore has announced V4 of its DSP architecture and a series of DSPs called SC2000 based on the V4 architecture
2013-07-23 Space qualified GHz-class RISC microprocessor
The PC7448 from E2v operates at speeds of up to 1267MHz and provides powerful floating-point computation capability when combined with an AltiVec engine.
2004-09-16 Royalty-free XAP RISC processor moves to 32bits
Cambridge Consultants has recrafted its XAP RISC processor architecture to handle up to 32bit data.
2009-02-11 RISC/DSP MCU aims at industrial, control apps
Hyperstone GmbH has introduced the E2, a 32bit RISC/DSP microcontroller with a programmable serial communication engine that is suitable for use in industrial sensing and control applications, and in cost-sensitive apps
2006-04-12 RISC processor integrates display controller
Toshiba announced the availability of the TX4961XBG-240, a 64bit RISC processor with integrated graphics and display controller
2003-05-09 RISC controller targets low-cost networking products
Toshiba Corp.'s T6TC1XB-0001 RISC networking controller is specifically developed for low-cost networking applications
2013-01-29 Phoenix-RTOS gets ported to eSi-RISC processors
EnSilica and Phoenix Systems' partnership expands the eSi-RISC ecosystem with an embedded RTOS that can use eSi-RISC's hardware MMU with memory protection and security features
2008-07-25 Omniscient C compiler boosts PIC32 RISC performance
HI-TECH Software took the wraps off an "omniscient" ANSI C compiler for 32bit MCU code that it claims boosts real-time response by more than 25 percent as well as nearly doubling code density.
2005-07-21 MIPS to discuss low cost RISC, DSP at ESC-Taiwan
MIPS Technologies Inc.'s media market development manager will discuss "RISC and DSP convergence: Increasing performance at lower costs" at this year's ESC-Taiwan to be held at Taipei's International Conference Center from July 27-28
2004-05-25 Marvell embedded MPUs to run on ARM architecture
Marvell has signed an agreement that enables them to produce a family of proprietary embedded microprocessors that will fully run the ARM architecture
2004-12-22 Intel strengthens Itanium architecture with HP design team
Intel Corp. has reached an agreement with HP to hire HP's Intel Itanium processor design team based in Collins, Colorado.
2003-10-31 Fujitsu develops CPU core for 32-bit RISC MCUs
Fujitsu Ltd has expanded its FR family of 32-bit RISC MCUs with the release of the FR80 processor core that is primarily used in digital home appliances
2011-06-02 EnSilica, Evatronix partner on eSi-RISC processor dev't
The deal will help EnSilica produce eSi-RISC processor subsystems with integrated peripherals while enabling Evatronix to expand its USB IP subsystem line to include RISC processor combinations
2008-11-03 Chips reembrace multicore architecture
DSPs are now beginning to reembrace multicore architectures, but mainly for specific applications possessing well-partitioned processing tasks.
2001-04-02 Bluetooth Architecture, Protocol And Applications
This paper examines the hardware architecture, software protocol and applications of a single-chip device that integrates Bluetooth radio and baseband, memory, a Harvard architecture RISC microcontroller and audio codec.
2004-11-24 Benchmarking the MAXQ instruction-set architecture vs. RISC competitors
This app note compares the MAXQ instruction set with competing microcontrollers, including the PIC16CXXX (mid-range devices), AVR, and MSP430.
2007-11-30 ARM-compliant processor offers low-power 32bit RISC
Faraday Technology has unveiled the FA606TE ARM v5 ISA-compliant processor that offers ultralow-power 32bit RISC with the synthesizable and configurable features
2005-02-01 Architecture options for convergent devices
Choose the right architecture that would help leverage multiprotocol flexibility in future handheld convergent devices
2012-04-19 32bit RISC Secure core based on Cortus APS3s CPU
StarChip's ARX CPU is targeted at the smart card market and is specifically designed to meet the requirements of embedded systems.
2001-12-01 Hybrid architecture for digital pictures
This paper describes the requirements involved in partitioning a hybrid SoC platform across a DSP for digital cameras.
2005-12-16 Building RISC cores with DSP enhancements
Merging DSP onto the main processor creates efficient system architecture with smaller area and lower power
2013-08-02 DCD's Soft IP core supports 8MB linear code space
The DP80390 boasts a pipelined RISC architecture executing up to 200 million instructions per second while supporting up to 8MB of linear code space and 16MB of linear data space.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

Back to Top