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2012-04-20 Verification platform geared for SoC, FPGA design
Mentor Graphics' Questa 10.1 release claims to increase productivity with regard to verification and boasts enhanced support of the Universal Verification Methodology
2011-05-16 Springsoft software adds advanced verification tech
Springsoft has integrated an advanced technology platform to its Certitude Functional Qualification System that will enable broader deployment of verification qualification methodologies
2002-04-15 Researchers propose dual design verification model
Indian researchers are proposing a novel verification methodology that uses two representations of a design throughout the verification process, one a behavioral model in C and the other an RTL model
2012-08-30 Overcoming challenges for SoC verification team
Know the unique problems that SoC verification engineers face and the approach that provides them a level of automation similar to that enjoyed by block-level verification teams
2006-06-01 Breaking the verification barrier
Startup OneSpin Solutions believes it has technology that will usher in a new era of IC formal verification. But if this company is successful, the real breakthrough may be one of bringing internal technology from a large integrated device manufacturer into a global, commercial EDA market
2009-10-05 Braving software-to-silicon verification challenges at 45nm
Software-to-silicon verification holds immense challenges at 45nm and beyond for system designers and tool vendors, with multiple paradigm shifts converging at the same time
2013-01-02 Apply formal methods to power-aware verification
Read about an apps approach for implementing formal methods to power-aware verification
2012-06-21 Acquisition expands Altrenta's RTL platform portfolio
Atrenta says that its acquisition of NextOp Software will accelerate its growth in front end design.
2004-05-18 0-In tool verifies metastability effects
Claiming a "breakthrough" solution for the automatic verification of metastability effects, 0-In Design Automation is preparing Archer CDC-FX, an addition to its clock-domain crossing (CDC) verification tool
2012-08-08 Grasping power awareness in RTL design analysis
Find out how formats such as CPF and UPF play a key role in capturing power intent for RTL design analysis and verification
2002-09-23 0-In Design: A preferred approach for verification
Companies designing complex multimillion gate ASICs recognize functional verification as one of the largest problems facing design teams
2003-08-12 Averant lands patent for checking design properties
RTL verification tool vendor Averant Inc. has been issued a new patent by the USPTO for its method of computing the design coverage of a set of properties
2003-08-08 Averant lands patent for checking design properties
RTL static functional verification tool vendor Averant has been issued a new patent by the USPTO for its method of computing the design coverage of a set of properties.
2013-05-09 Why stitch and ship is no longer workable
As the systems change, the stitch and ship methodology is leading to increased numbers of costly failures.
2015-11-23 What makes hardware emulation so compelling
Here is a quick assessment of the evolution of hardware emulators over the past two decades, comparing where things stood in the 90s to where they are today.
2005-06-01 OEMs to EDA world: Time to catch up
If the EDA industry provides tools on time, it will continue to be a growing market, says Dataquest analyst.
2015-03-26 Understanding design compilation in hardware emulators
Design capacity in hardware emulators, also the compilation flow, is heavily dependent on the type of technology utilised in the verification engine
2014-11-20 The ways to verify SoC
In this article, we will start with the discussion on what and why of verification and only then consider the how
2003-05-30 O-In offers 'unified coverage' metric
Claiming to offer the first metric that measures verification in both simulation and formal tools, 0-In Design Automation has announced a &quot:unified coverage" metric called structural coverage
2014-11-18 Addressing the problem of X unknowns in simulation
The sheer complexity and common use of power management schemes raise the probability of an unknown X state in the design, translating into a functional bug in the final chip
2013-02-06 Solving SoC and FPGA prototyping debug issues
Read about the accelerated development, verification and debugging of ASIC hardware and software
2002-10-02 Choosing an IP core
IP cores allow design teams to rapidly create large SoC designs by integrating pre-made blocks that do not require any design work or verification
2011-10-24 Overcome challenges of ASIC/SoC prototyping with FPGAs
Learn about FPGA-based prototyping and the various factors that must be taken into account to successfully implement a prototyping strategy.
2008-08-01 Multithreading comes undone
EDA vendors have struggled to meet the challenge of multicore IC design by rolling out multithreading capabilities for their tools. Nonetheless, the question cannot be ignored: Is multithreading the best way to exploit multicore systems effectively?
2012-04-30 Design for power methodology: From architectural plan to signoff
Here's a look at a holistic design for power methodology that spans from architectural decisions through front-end design to physical implementation and sign-off.
2014-09-11 When sub-systems are more than just bigger IP
At the end of the day, the reason CPU and GPU sub-systems are not just bigger IP is that they have to be wrapped and optimised to the nth degree to be competitive on Power, Performance, Area/Cost, and Reliability.
2015-09-21 Hybrid emulation: A practical solution
In this article, we show how the hybrid combination of virtual platform and FPGA hardware offers a best-of-both-worlds approach.
2014-02-13 Energy design through unified hardware abstraction
Learn how to achieve energy-efficient solutions through optimal alignment across the pre- and post-silicon phases of energy optimisation supported by unified design flows, abstractions and formats.
2012-10-19 Employ hierarchical methods for power intent specification
Here's a guide to using a hierarchical low-power design methodology.
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