Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > rtl-to-gdsII

rtl-to-gdsII Search results

total search121 articles
2007-04-02 Synopsys design platforms support UPF 1.0
Synopsys Inc. has announced a low-power design flow that will implement the Accellera Unified Power Format version 1.0 in its IC verification and implementation products in the second half of 2007.
2009-03-19 Synopsys CEO confident of IC rebound
Synopsys Inc. chairman and CEO Aart de Geus touted the company's new products and said the semiconductor industry would remain critical to the world after emerging from a recession expected to be long and deep.
2004-01-01 Startups taking over ESL
It is very frequent that there a lot of new startup in ESL design, and ESL announcements from small, established EDA vendors.
2006-03-29 STARC adopts Synopsys' IC compiler to boost efficiency
Synopsys Inc. announced that STARC has adopted its IC Compiler in the newly released STARCAD-21 V3.0 production flow.
2007-02-15 ST adopts Synopsys compiler for ASIC design
STMicroelectronics has deployed Synopsys Inc.'s Design Compiler topographical technology in its 90nm and 65nm ASIC design flow to eliminate design iterations and streamline the overall design cycle for its internal design groups and external customers.
2011-02-07 Solution speeds billion-plus gate design at 28nm
Cadence Design Systems Inc. has announced that it is advancing the design of giga-gate/gigahertz SoCs with digital end-to-end flow at 28nm.
2011-01-20 SoC design solution optimized for HKMG tech
Synopsys Inc. announced that it is delivering a low-power, high-performance SoC design solution optimized for the Common Platform alliance (CPA) 28nm high-k metal gate (HKMG) technology.
2009-04-23 Sign-off flow to speed up product dev't
Taiwan Semiconductor Manufacturing Co. Ltd has rolled out a mixed-signal/RF design kit and a foundry-specific integrated sign-off flow designed to accelerate product development process.
2002-05-09 Samsung endorses STA in BuildGates, Cadence PKS software
Samsung Electronics Co. Ltd has issued a sign-off endorsement for the static timing analysis (STA) technology embedded within BuildGates synthesis and Cadence Physically Knowledgeable Synthesis (PKS) software for ASIC design flows.
2006-05-16 Running start helps clear 90nm hurdles
Back in 2004, fabless IC maker Sandbridge Technologies couldn't get the performance it needed at the 0.13?m process node. The wireless-telecom player took a risk and became one of the first companies to try the relatively untested 90nm node.
2006-06-19 Renesas Vietnam selects Synopsys as EDA provider
Synopsys announced that Renesas Design Vietnam has chosen Synopsys as its EDA provider for SoC design.
2005-08-03 Renesas confirms silicon success on automotive MCU
Renesas Technology Corp. has achieved first-pass silicon success on a car audio microcontroller developed using Magma Design Automation Inc.'s software.
2005-12-07 P.A. Semi's 65nm processor developed with Cadence platform
Cadence said its Encounter digital IC design platform has helped P.A. Semi develop its new 65nm multicore PWRficient processor with a successful test-chip tapeout in March 2005.
2005-01-28 Marvell obtains silicon success using Magma design solutions
Magma Design Automation Inc. announced that Marvell Technology Group Ltd has achieved silicon success on several designs using Magma's Blast Create and Blast Fusion software.
2006-09-12 Magma, SMIC partner on 90nm ref flow
Magma Design Automation and SMIC announced the availability of an advanced IC implementation reference flow for SMIC's 90nm low-power process.
2007-03-12 Magma touts first parallel fast Spice
Magma Design announced the availability of the FineSim Pro Parallel Manager, claimed to be the first parallel fast Spice capability targeting the verification of large mixed-signal SoCs.
2007-03-05 Magma tools cut clock tree power draw by 25%
Magma Design Automation has introduced a pair of low-power IC implementation and analysis tools that the company claims have been shown to reduce power consumption in nanometer ICs by 25 percent.
2004-01-20 Magma to focus on silicon compilation
During a recent visit to India chairman and CEO Rajeev Madhavan affirmed that Magma Design Automation will soon offer an automated silicon compilation system.
2004-05-21 Magma to expand into structured ASICs, FPGAs
Magma Design is turning its attention to FPGAs and structured ASICs with the release of new products in its Blast line targeting those markets.
2005-11-23 Magma partnering with Indian university on EDA training
Magma Design Automation Inc. said Monday (Nov. 21) that its Indian subsidiary has entered into a partnership with one of India's top schools, Anna University, in a push to help increase number of professionals trained on state-of-the-art EDA tools.
2004-09-23 Magma panelists explore whether DFM is the real deal
After much bravado, EDA vendors like Magma Design Automation and Mentor Graphics are starting to deliver viable design-for-manufacturability tools, or DFM-savvy tools.
2005-08-25 Magma kicks off MUSIC users conference series
The ongoing 2005 Magma Users Summit on Integrated Circuits (MUSIC) in Banglore, India discusses common problems and solutions related to design and manufacturing of ICs.
2004-02-27 Magma buys IC verification startup Mojave
Moving aggressively into the design for manufacturability (DFM) market, Magma Design Automation announced Tuesday (February 24, 2004) that it will acquire Mojave Design, a much-awaited startup launched by former Avanti Corp. executives.
2005-04-07 Logic synthesis 'dying'
Standalone logic synthesis will disappear and fold into physical design, said Rajeev Madhavan, Magma Design Automation CEO, at a keynote speech.
2013-03-15 Issues in using 3rd party IP in ASIC/SoC design
Know some of the common challenges in integrating and using 3rd party IPs in today's high-end ASIC/SoCs.
2002-03-21 Interoperability: a sore point for tool suppliers, users
Strongly divergent views of EDA interoperability surfaced at a panel discussion at the International Symposium on Quality of Electronic Design, as users called for open standards and vendors expressed skepticism of such efforts.
2005-12-20 Inphi tapes out high-speed chip with Cadence platform
Cadence announced that Inphi has successfully taped out a complex high-speed chip using the Cadence Encounter digital IC design platform.
2011-02-03 Implementation platform addresses Gigascale design
Synopsys Inc. releases the 2010.12 Galaxy Implementation Platform that addresses the scalability, convergence and throughput needs of gigascale IC design.
2003-10-09 IEEE approves ALF, synthesis standards
Paving the way for greater library and EDA tool interoperability, IEEE has approved Accellera's Advanced Library Format and Verilog and VHDL synthesis subsets.
2002-11-07 IC layout tools grow while front-ends decline in '01
IC implementation toolsets and IC layout tools experienced phenomenal growth in 2001, while front-end tools such as logic synthesis faltered, according to a new report by Gartner Dataquest.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

Back to Top