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2007-02-05 IEEE okays Synopsys' SPEF proposal
The IEEE 1481 working group has approved Synopsys Inc.'s proposal for an extension to the standard parasitic exchange format for process and temperature variation.
2004-04-23 Timing optimization rolls for logic designers
Silicon Dimensions has released an add-on to its Chip2Nite floor planner, block design and analysis offering.
2015-11-11 Synopsys, GlobalFoundries team up for 22nm FD-SOI sol'n
The Synopsys Galaxy Design Platform, enabled for the GlobalFoundries' 22FDX platform, claims to offer FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies.
2005-09-01 Startup puts team to work on the data explosion
Edxact SA comes out with a tool that accurately provides netlist reduction for parasitic netlist elements.
2004-06-03 Silvaco offers full-chip RC extraction
Silvaco International has released Hipex, which claims "3D accurate" resistance and capacitance (RC) extraction.
2002-12-11 Nassda aims Critic timing technology at ASICs
Extending its fast circuit-simulation technology into digital design, Nassda Corp. has claimed a breakthrough with a transistor-level, full-chip, dynamic timing analyzer.
2006-12-04 Clear Shape offers electrical DFM analysis solution
Clear Shape Technologies has announced OutPerform, said to be the first complete and silicon-correlated electrical DFM analysis and optimization product to enable designers using sub-90nm processes to control the impact of lithography, mask, etch, RET, OPC and CMP effects on their chip parameters.
2014-08-25 Are multi-patterning corners necessary for 16/14 nm?
Multi-patterning is the technique required for printing geometries that are smaller than the wavelength of light used in manufacturing can accurately resolve. Find out if it is indeed needed for 16-nm and 14-nm nodes.
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