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2007-03-16 Signal-integrity issues plague multigigahertz era
Engineers want a new bag of tricks to manage signal integrity as data rates soar into multigigahertz territory.
2005-01-17 Serial buses cut EMI, cabling constraints in 3G cam phones
Serdes plays a role in reducing cabling constraints and EMI when interfacing cameras and LCDs to baseband processors in mobile phones.
2001-10-16 Reinventing the switch fabric architecture
This article features the functions of the new switch fabrics designed to solve bottlenecks and minimize QoS concerns in edge access switching systems.
2002-11-20 Quake crafts 10Gb transceiver in SiGe
Quake Technologies has unveiled a serial transceiver that targets 10.3Gbps IEEE 802.3ae Ethernet and 10.57Gbps Fibre Channel system designs.
2009-06-08 PRBS mode setup for the MAX9257/MAX9258 evaluation kit
This application note details how to use the internal BER testing (BERT) feature of the MAX9257/MAX9258 Serdes in its pseudorandom bit sequence (PRBS) mode.
2003-12-16 PLLs, DLLs becoming reusable IP
PLLs and DLLs are becoming increasingly important in the SoC design and are gradually turning into IP that can actually be reused by ordinary mortals.
2007-04-02 PCIe switch line is on the move
PLX Technology Inc. has rolled out three new chips that expand its line of PCIe switches to 13 devices.
2004-09-30 PCI Express requires ATE strategy
As PCI Express becomes mainstream, IDMs and fabless companies require a new breed of production test strategies.
2003-09-09 Pacific Digital adopts Agere interconnect technology
Pacific Digital Corp. has integrated Agere Systems Inc.'s interconnect technology into its next-gen host adapter for SAN apps.
2004-11-01 Options emerge for 10Gbps chip-to-chip interfaces
When selecting a chip-to-chip interface, consider factors such as size, power, latency and the number of required package signal balls.
2003-03-13 Oki extends collaboration ties with UMC
Oki Semiconductor has joined United Microelectronics Corp.'s Gold IP program and Design Plus partnership which will allow Oki access to UMC's 0.155m process and intellectual properties.
2004-09-01 No 'magic bullet' for signaling schemes
While PAM-4 may have an advantage for very high-loss channels, this advantage is not universal.
2007-04-02 New tech pares down I/O power draw
Rambus Inc. and a group of leading academics have set a high-water mark in bringing fast chip-to-chip links into the era of low-power design.
2005-08-22 New HyperLynx version available from Mentor Graphics
Mentor Graphics announced the latest version of its powerful and easy-to-implement tool suite for pre- and post-layout signal integrity simulation and analysisHyperLynx 7.5.
2003-03-14 NEC expands silicon platform for high speed interfaces
NEC Electronics has expanded its 0.15?m Instant Silicon Solution Platform with the addition of two new base arrays and a 3.125Gbps serdes.
2002-02-05 National Semiconductor bridge addresses 248 PHY ports
Supporting full bidirectional Utopia, the DS92UT16 Utopia-LVDS bridge features an extended cell support and built-in address translation, enabling the device to address as many as 248 PHY ports.
2002-02-07 National LVDS ICs targeted at telecom, datacom apps
The company announced the availability of Boundary SCAN-compliant LVDS chips designed for telecom and high-speed data communication applications.
2003-01-22 Mysticom quad PHY transceiver consumes 0.6W
The MY1104E GbE quad PHY transceiver provides four serdes channels with speed ranges from 1Gbps to 1.25Gbps.
2010-01-22 Mux ups test instruments' generator data rate
Agilent Technologies has released the N4876A 2:1 mux, extending the generator data rate of its J-BERT N4903B and ParBERT 81250A test instruments up to 28Gbit/s.
2003-05-23 Multilink transceivers target switch fabric systems
Multilink Technology has expanded their PHYreSTORM family of datacom serdes devices with the introduction of the MTC1138 10Gbps transceiver.
2003-06-25 Marvell, Dune partner on GbE chipset
Marvell Semiconductor has paired its packet processor, classification and serdes technology with Dune Networks' traffic management technology.
2001-08-09 LVDS: Five tips for buffering signal integrity
This conference technical paper provides general LVDS design tips and shows how National Semiconductor's new buffers can improve signal quality in existing applications.
2006-02-14 LVDS deserializers reduce EMI
Maxim introduced the latest members of its high-speed LVDS SerDes family, which are hot-swappable, 21-bit, DC-balanced LVDS deserializers with programmable spread spectrum.
2004-10-18 LSI Logic takes aim at PCI Express
Targeted to the needs of PCI Express developers, LSI Logic announces a new family in its RapidChip structured-ASIC line.
2005-03-22 LSI Logic ASIC aids developers
LSI Logic's new RapidChip Xtreme2 family of Platform ASICs promises to provide the necessary resources for developers to tackle the demanding high-speed serial apps.
2010-06-22 LatticeECP3 and LatticeECP2M high-speed backplane measurements
This technical note outlines two experiments that measure the serdes backplane transmission performance thresholds of the LatticeECP3 and LatticeECP2M devices.
2002-07-18 Lattice to acquire Cerdelinx
Lattice Semiconductor Corp. has entered into an agreement to acquire privately-held Cerdelinx Technologies Inc.
2003-04-07 Lattice selects Agilent tool for FPGA, FPSC products
Lattice Semiconductor Corp. has purchased Agilent Technologies Inc.'s multiple 93000 test systems to test a variety of its products.
2004-02-18 Lattice P core eyes PCI Express apps
Lattice Semiconductor has released an IP core for next-generation PCI Express applications.
2002-08-30 Lattice completes acquisition of Cerdelinx
Lattice Semiconductor Corp. has completed the acquisition of Cerdelinx Technologies Inc.
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