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2007-09-04 Oscilloscope-based DDR3 compliance software debuts
Agilent Technologies Inc. says it has developed the industry's first oscilloscope-based DDR3 compliance test application.
2006-10-19 Optimal announces enhancements to SiP analysis suite
Optimal is announcing chip/package/PCB co-design support in the form of enhancements to its Optimal SiP Analysis Suite.
2005-06-01 OEMs to EDA world: Time to catch up
If the EDA industry provides tools on time, it will continue to be a growing market, says Dataquest analyst.
2005-08-22 New HyperLynx version available from Mentor Graphics
Mentor Graphics announced the latest version of its powerful and easy-to-implement tool suite for pre- and post-layout signal integrity simulation and analysisHyperLynx 7.5.
2003-06-18 NEC design flow to improve wiring delay estimation
NEC Electronics Corp. and its subsidiaries NEC Electronics America Inc. and NEC Electronics GmbH have developed a new copper-interconnect modeling methodology.
2004-03-04 Nassda simulator gets analysis tools
Nassda Corp. has announced a complete nanometer analysis platform with the release of HSIM v5.0.
2003-11-03 Move beyond the legacy of IR drop
Chang warns SoC designers to move beyond the IR-drop legacy and its oversimplifications.
2006-02-13 Mentor releases new design kits for Intel's IBIS 4.1 AMS models
Mentor Graphics announced the release of the ICX and ICX Pro Signal Integrity design kits for Intel's next generation I/O controller hub. These kits are said to be the first to utilize Intel's new IBIS 4.1 and IEEE 1076.1 standard VHDL-analog/mixed-signal models
2004-11-12 Mentor PCB tools support Xilinx FPGA transceiver tech
Mentor Graphics Corp. and Xilinx have announced a collaboration in which Mentor will supply its PCB tool users with reference data allowing them to more easily implement the multi-gigabit transceiver (MGT) technology available in Xilinx FPGA on their printed circuit board (PCB) designs
2004-11-16 Mentor PCB tools support Xilinx FPGA MGT technology
Mentor will supply its PCB tool users with reference data allowing them to more easily implement the MGT technology in Xilinx FPGA on their PCB designs
2006-09-18 Leakage takes priority at 65nm
As the first reports on 65nm design come in, the good news is that there seems to be no problems at 65nm that weren't present at 90nm. The bad news is that some of the problems that plagued 90nm get much worse at the new node.
2004-06-22 Grid software firm seeks role in global design
Electronic design activities are moving to places like mainland China and India after bursting of bubble.
2004-06-01 Full-wave analysis tools target 2GHz+
Optimal releases a series of tools for 3D full-wave signal integrity simulation, analysis and verification for high-speed IC, package and PC-board designs
2006-07-19 EDA startup rolls out analysis suite for 65nm and below
Startup Anova Solutions created a new EDA tool suite to analyze process and design variations to maximize yield and performance in 65nm and below designs
2002-02-05 DesignCon panel explores deep submicron challenges
Two user panelists and two EDA vendor panelists discussed the challenges of deep submicron, 50-million-transistor chips at a panel in the DesignCon 2002 conference.
2015-01-29 Design solutions accelerate design signoff, analysis
The Sigrity Parallel Computing 4-pack and the Sigrity System Explorer from Cadence claim to speed up product creation efficiency by improving signoff-level PCB extraction accuracy.
2012-04-30 Design for power methodology: From architectural plan to signoff
Here's a look at a holistic design for power methodology that spans from architectural decisions through front-end design to physical implementation and sign-off.
2004-03-16 Co-design strategies tame PC system bus
The design of high-speed buses is only possible through the use of the proper EDA tools and effective methods, such as DOE, to co-design the entire bus.
2002-07-01 Closing the custom gap
Why are custom circuits faster than equivalent ASICs, and what can be done to narrow the difference? That's the topic of the new book: "Closing the Gap Between ASIC and Custom."
2002-05-22 Cadence overhauls IC implementation suite
Aiming to speed timing closure and signal integrity analysis, Cadence Design Systems Inc. this week will announce an across-the-board update to its SP&R (synthesis, place and route) IC implementation suite
2002-09-23 Cadence adds Plato routing engine to design flow
Cadence Design Systems Inc. is upping the ante in the RTL-to-GDSII IC design tool arena with the latest release of its SoC physical implementation tool
2005-06-01 Big speedup promised in library characterization
Library characterization has long been an arcane art, but startup Z Circuit Automation aims to change this.
2005-09-06 AWR to acquire design tools group APLAC
Applied Wave Research Inc. is expected to announce Tuesday (Sept 6) that it is buying, for an undisclosed sum, APLAC Solutions Corp OY, a company specializing in analog and RF simulation tools for wireless applications.
2009-02-06 Agilent rolls million-bit-per-minute SI simulator
Agilent Technologies Inc. has developed a million-bit-per-minute SI Channel Simulator for multigigabit chip-to-chip data link design.
2007-01-30 Agilent intros new digital communications analysis tools
Agilent Technologies has introduced a phase noise application software and new options for the digital communications analyzer.
2003-10-01 A rebirth of IC compilation
R. Goering rediscovers an old paradigm for designing sub-100nm ICs in an interview with Rajeev Madhavan, Magma Design Automation's CEO: silicon compilation.
2005-02-01 10x 'fast SPICE' speedup promised
Nascentric vows to fill the gap in the 'fast SPICE' market left by Nassda acquisition.
2005-03-30 'Concurrent' IC design suite rolls
Synopsys rolled out IC Compiler, which concurrently runs physical synthesis, clock tree synthesis, placement, routing, yield optimization and signoff correlation.
2005-06-06 Zuken claims 3-D routing checker cuts design time up to 6 weeks
Zuken has introduced a two- and three-dimensional routing checker for high-voltage PCBs that the company claims cuts typical design time by six weeks
2012-08-15 Optimize dynamic power signature of digital ICs to reduce power noise
At advanced process nodes, the biggest hurdle to achieving power noise integrity lies in handling high frequency power demand
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