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2012-06-07 Why active probes are worth buying
Although active probes are more expensive than passive ones, they offer a superior level of performance that may be essential in certain circumstances.
2004-11-01 When custom ASICs aren't the answer
Given their lower costs at high volumes, custom ASICs would be the logical choice. But that's often not the case.
2001-05-01 Vendors should count silicon, not tapeout wins
Tapeouts are certainly important. But they are not an end unto themselves, but, rather a milestone on the way to the goal of working silicon.
2003-12-18 UMC says design methodology reduces simulation time
By providing detailed, foundry-specific modeling for RF components, United Microelectronics Corp. claims it can reduce electromagnetic simulation time from a matter of hours to minutes. The company's new Electromagnetic Design Methodology (EMDM) is aimed at customers designing RF CMOS ICs.
2012-10-17 TSMC names EDA partners for CoWoS, 20nm
TSMC has validated technologies from Cadence, Mentor and ANSYS for use in its 20nm and CoWoS design infrastructure.
2012-10-05 Troubleshoot, verify 8b/10b encoded signals with real-time scope
Test equipment with features designed for serial bus test can dramatically improve productivity and lead to more reliable, higher performing designs.
2014-04-09 Troubleshoot, fix problems on the go
Know how particular oscilloscopes can be used to capture and isolate waveform anomalies to identify source of the problems.
2012-07-09 Tektronix simplifies serial bus debug
Tektronix rolls out upgrades that simplify serial bus debugging.
2013-02-04 Tackling the challenges of transition to DDR4
Know the key technical challenges designers face in transitioning to DDR4.
2004-10-05 System level design is here, Synopsys CTO says
System level design is happening now but it remains to be seen whether it will become EDA's next big thing.
2005-02-07 Synopsys verification tools to face tough IP design challenges
Chipidea has licensed key tools included in Synopsys Inc.'s Galaxy design and Discovery verification platforms to address tough IP design challenges.
2008-07-01 Synopsys gears up for 'techonomic' challenges
According to chairman and CEO of Synopsys Aart de Geus: There's a trade-off between innovation, execution and collaboration. You can execute, but if you don't collaborate with the right people, you have nothing.
2006-06-30 Synopsys expands test portfolio with NanoTime
Synopsys has announced the availability of NanoTime, a next-generation transistor-level static timing analysis solution.
2004-03-31 Synopsys CEO defends MoSys acquisition
Responding to user questions on a variety of topics, Aart de Geus, Synopsys CEO, defended his company's proposed acquisition of MoSys in a new E-Mail Synopsys User's Group (ESNUG) mailing.
2008-03-17 Succeed at 65nm design
A true DFM-aware environment accounts for process variability and lithographic effects in the context of timing, power, noise and yield at every stage of the flow. This begins with the characterization of the cell library, continues through implementation, analysis and optimization, and ends with sign-off verification.
2008-05-22 Storage solution designed for Virtex-5 FPGAs
Xilinx has announced a flash-based configuration and storage solution for the Virtex-5 family that delivers new levels of configuration performance for meeting today's high-speed connectivity requirements.
2003-08-19 Startup turns to China for analog design suite
Paragon IC Solutions is a two-year-old EDA startup that's selling an analog IC design suite with a 13-year heritage.
2006-01-02 Startup promises DFM-aware IC router
Startup Pyxis Technology Inc. has announced plans to field a design-for-manufacturability-aware IC router.
2004-03-01 Starc to release Starcad-21 design methodology
Semiconductor Technology Academic Research Center will release v1 of a chip design methodology that covers silicon implementation from RTL to GDSII.
2013-02-06 Solving SoC and FPGA prototyping debug issues
Read about the accelerated development, verification and debugging of ASIC hardware and software.
2001-06-01 Silicon prototyping verifies IP functions
SoC designers are confronting several important tasks in optimizing next-generation products. New systematic approaches are needed to ensure that IP can be transferred from one process geometry to the next.
2006-10-26 Sigrity unveils new IC package characterization suite
Promising a new suite of tools that will enable 'fast, easy, accurate and complete' IC package characterization, Sigrity Inc. this week is releasing its SpeedPKG Suite.
2002-09-05 Sequence, UMC address interconnect inductance issues
Sequence Design and UMC have partnered to complete the first silicon correlation of an interconnect self inductance parasitic modeler.
2002-10-04 Sequence Design: Taiwan primed for growth
In my view, one of the driving forces behind this robust IC design community is Taiwan's consistently strong systems-design industry. While Taiwan remain resolute proponents of a global supply chain, there seems to be a great deal of interest and investment going towards developing local sources for ICs that leverage the island nation's native engineering talent and state-of-the-art fab capacity.
2006-05-16 Running start helps clear 90nm hurdles
Back in 2004, fabless IC maker Sandbridge Technologies couldn't get the performance it needed at the 0.13?m process node. The wireless-telecom player took a risk and became one of the first companies to try the relatively untested 90nm node.
2002-06-05 RTL-to-GDSII flow shows signs of maturity
The RTL-to-GDSII design flow will take center stage at next week's Design Automation Conference in New Orleans, as several vendors show new technologies intended to solidify an all-in-one flow.
2003-09-16 Redefining design for yield, manufacturability
By adopting a more design-driven approach to production, many of the yield and manufacturing issues daunting the semiconductor industry can be addressed before they even occur.
2004-04-13 PTC acquires product life cycle vendor
In an apparent step toward linking mechanical CAD with EDA, mechanical CAD and product life cycle management (PLM) software vendor Parametric Technology Corp. (PTC) has acquired EDA data-centric PLM vendor OHIO Design Automation Inc. for about $12 million.
2011-12-15 Prototyping: Virtual vs physical
Simulating and analyzing the products in software during the design process provides significant time-to-market and quality advantages over older practices of producing multiple physical prototypes and testing them in the lab.
2011-02-04 Protocol analyzer eases DDR3 memory system design
Le Croy Corp. demonstrated four products at DesignCon2011: a protocol analyzer targeting DDR3, another protocol analyzer featuring small size and low ocst, an interposer card and a mezzanine card.
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