Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > Sigrity

Sigrity Search results

?
?
total search19 articles
2006-02-15 Synopsys licenses IC package design tech to Sigrity
Sigrity announced the acquisition from Synopsys of a worldwide perpetual unrestricted license to advanced single- and multi-chip IC package design technology, including technology embodied in Synopsys' Encore products.
2006-10-26 Sigrity unveils new IC package characterization suite
Promising a new suite of tools that will enable 'fast, easy, accurate and complete' IC package characterization, Sigrity Inc. this week is releasing its SpeedPKG Suite.
2005-06-02 Sigrity tools focus on IR drop analysis for packages and boards
Sigrity introduced early this week two standalone tools customized for analysis of voltage drop, or IR drop, on packages and PCBs
2007-05-01 Sigrity tool automates decap selection
Sigrity Inc. claims a breakthrough with its tool that helps automate the selection and placement of decoupling capacitors.
2007-01-17 Sigrity ports signal integrity tools to Linux platforms
Sigrity Inc. has ported its power and signal integrity tools to 64-bit Linux platforms, promising to speed signal-integrity analysis for chip, package and board applications.
2006-02-09 Sigrity acquires Synopsys' Encore technology
Sigrity disclosed that it has acquired single and multi-chip IC package design technology from Synopsys, including the technology within the Encore design and analysis tool. Financial terms of the agreement were not disclosed.
2012-07-03 Cadence acquires Sigrity, strengthens system development
Cadence Design Systems has acquired Sigrity with the aim of boosting their Allegro and OrCAD design tools.
2004-07-01 Tool analyzes power across IC, package
Sigrity's XcitePI simulates power grids on the package plane to examine power integrity issues occurring between ICs and packages.
2004-01-20 Electromagnetic simulator links to HSpice
Offering a co-simulation capability for PCB and IC package design, Sigrity Inc. is announcing that its Speed2000 electrical analysis software now runs with Synopsys' HSpice analog simulator.
2009-02-02 Analysis solution provides precision for serial links
Sigrity Inc has introduced Channel Designer, an analysis solution that offers the flexibility and accuracy required for high-speed serial links.
2006-05-16 A review of PCB-level power delivery system
Improve power delivery system performance by understanding the fundamental issues in design, and doing extensive modeling and simulation of the entire PDS.
2015-01-29 Design solutions accelerate design signoff, analysis
The Sigrity Parallel Computing 4-pack and the Sigrity System Explorer from Cadence claim to speed up product creation efficiency by improving signoff-level PCB extraction accuracy.
2012-07-05 Cadence buys signal analysis provider
The acquisition of Sigrity Inc. brings to Cadence analysis technologies that will combine with Allegro and OrCAD design tools to provide a comprehensive front-to-back integrated flow that will enable system and semiconductor companies to deliver high-performance devices employing gigabit interface protocols such as DDR and PCIe.
2012-10-17 TSMC names EDA partners for CoWoS, 20nm
TSMC has validated technologies from Cadence, Mentor and ANSYS for use in its 20nm and CoWoS design infrastructure.
2006-09-18 PCB designers struggle with cost issues
With PCB designs getting faster and more complicated, designers are starting to fret about signal integrity, thermal issues and EMI. But respondents to the PCB portion of the EE Times 2006 EDA Users Survey said that meeting cost budgets is their greatest concern.
2007-10-09 Master the I/O planning puzzle
Systemwide I/O planning is an exercise in coordinating device placement with associated pin and net assignments across the chip-package-board system to maximize system quality for the target application. Achieving this goal is a multidomain balancing act of tradeoffs and iterations.
2005-08-17 Easier EMC simulation anyone?
Flomerics released Version 6 of its integrated analysis environment for physical design of electronics, with improved communication between thermal and electromagnetic compatibility simulation.
2004-03-16 Co-design strategies tame PC system bus
The design of high-speed buses is only possible through the use of the proper EDA tools and effective methods, such as DOE, to co-design the entire bus.
2013-03-13 Cadence to boost SoC offerings with Tensilica buyout
Cadence Design Systems has agreed to purchase Tensilica for approximately $380 million to expand its scope of IP offerings and accelerate delivery of IP roadmap.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top