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2008-04-21 SoC complexity, cost compel companies to collaborate
Growing complexity and the staggering costs associated with designing SoCs are forcing companies to seek collaboration on a variety of IP issues.
2005-08-30 SoC collaboration network signs agreement with CSIP
Design and Reuse (D&R), a global collaboration network for sharing system-on-chip (SoC) design resources, said Friday that it has formed a partnership with China Software and Integrated Circuit Platform (CSIP).
2003-03-03 Selecting a CPU core for multi-CPU SoC designs
This article examines the many features of processor cores being considered for multi-CPU designs.
2012-02-10 Samsung, Cadence partner in nanometer SoC design
The companies will collaborate on a design-for-manufacturing (DFM) infrastructure to tackle physical signoff and electrical variability optimization for 32, 28 and 20nm ICs
2005-10-27 Samsung senior VP to keynote on memory at SoC conference
Jon Kang, senior VP of the Technical Management Group at Samsung Semiconductor, will deliver a keynote address on semiconductor memory at the 3rd International System-on-Chip (SoC) Conference and Exhibition happening this November
2004-09-21 Samsung methodology reduces SoC design time
Samsung revealed a hardware/software co-design methodology that it claims will reduce overall design time for the company's SoC products by up to 40 percent.
2013-12-03 RTL signoff: A design imperative
"RTL Signoff" as an established concept has gained significance in the last year. However, writes Atrenta's Piyush Sancheti, does a commonly accepted definition of RTL signoff exist?
2004-10-08 Rohm design platform based on CoWare ConvergenSC
Rohm developed a platform named Real Platform based on CoWare's ConvergenSC, a System C-based SoC design environment for ESL design.
2003-04-25 Ricoh to deploy Monterey design flow in Japan
Ricoh Co. Ltd has purchased an entire line of Monterey Design Systems' planning, prototyping, and implementation tools for immediate use in Japan
2006-06-26 Reusable virtual components gain popularity with SoC
The crash of 2001 spelled disasters for pure IP companies who had not yet established brand loyalty. Many were bought out by more established companies, while others simply shut down for lack of revenues.
2003-09-16 Register-transfer level design handoff is ready
Shrinking process nodes and tightened purse strings have made the venerable "gate-level design sign-off" unacceptable
2014-11-18 Reducing SoC power: Where should the focus be
Typically, efforts to manage power consumption in SoC design are focused on the CPU and GPU. The SoC interconnect is one area that needs to be re-evaluated.
2014-12-09 Reduce power SoC consumption in the interconnect
Here's a modular approach to SoC interconnect for reducing power consumption. The modular concept is different because it consists of a distributed architecture of various components
2008-10-01 Reap the rewards of package-aware design
Chip designers must consider package routability, power delivery and I/O behavior during the initial I/O planning process. To do so, they should combine package-aware I/O planning with automated floor-plan synthesis, which can be very cost-effective for the chip floor plan and the package layout.
2006-09-18 Re-thinking SoC design at 65nm, below
Executives from major IC houses and EDA companies have been talking about the design challenges facing developers as SoC designs move from 65- to 45- and 32nm.
2009-03-11 R3Logic to advance 3D design flow R&D
R3Logic announced that it has created a new R&D center in Grenoble, France to develop and enhance its design tools for 3D heterogeneous system and system-in-package design
2008-02-11 Putting the system in electronic system design
The narrow scope of most ESL approaches and tools has limited their adoption. A more encompassing methodology, one that steps beyond the SoC, is needed to dramatically reduce time, cost and errors in complex system development
2003-05-08 Pulsic upgrades IC design toolset
Pulsic Ltd has announced a new release of its Lyric Physical Design Framework
2013-05-28 ProximusDA, ST team up for SoC TLM virtual prototypes
The collaboration combines ProximusDA's expertise in parallel code distribution with ST's deep knowledge of Transaction Level Modelling and advanced distributed-computing architecture.
2002-04-10 Procket Networks adopts Avant! technology for SoC design
Procket Networks Inc. has selected Avant!'s Astro optimization, place-and-route technology for its gate SoC designs
2011-09-19 Power Silicon's SoC design earns patent win
Open-Silicon has earned a patent win for its low power ASIC design process through design-specific library augmentation
2006-04-03 Platform-based SoC design comes of age
Ongoing silicon scaling has prompted the IC industry to seek new design methodologies, the most notable of which is platform-based SoC design.
2002-05-28 Pixelworks selects Avant!'s JupiterXT, SinglePass-SoC
Fabless semiconductor company Pixelworks, has selected Avant!'s JupiterXT hierarchical design planning and the SinglePass-SoC design-closure solution to design its next-gen SoC products.
2013-08-08 Peripheral hub as backbone of efficient SoC design
Know the ways to integrate digital, analogue, routing, and interconnect sub-systems into an ARM-based SoC embedded system
2002-10-16 Passing the SoC test with flying colors
The key concern of product developers, SoC design houses and wafer fabs is to provide higher performance and functionalities of SoC at the lowest cost.
2005-12-21 Partnership targets SoC designs in Greater China
ARC and Global Unichip's new partnership aimed at speeding time-to-market for Greater China's increasing number of fabless startup companies attacking the digital audio IC market.
2004-03-26 Panelists cite shortcomings of process design kits
The process design kits (PDKs) issued by foundries to chip designers are difficult to keep current, and may place too much reliance on design rules, according to panelists at the International Symposium on Quality Electronic Design (ISQED) here March 22, 2004
2012-08-30 Overcoming challenges for SoC verification team
Know the unique problems that SoC verification engineers face and the approach that provides them a level of automation similar to that enjoyed by block-level verification teams
2011-02-07 Overcome smart utility meter design challenges
Know the major issues of metering SoC design and the proposed solutions to achieve the intended goals.
2010-07-28 Optimizing power in SoC designs
Current methods employed by designers for optimizing power are inefficient and unproductive, making it difficult to know when a design is fully power optimized
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