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2009-02-03 Synopsys, ST team up on SI sign-off tools
Synopsys Inc. and STMicroelectronics have agreed to join forces to accelerate the development of methodologies and flows for low-power and high-performance SoC timing sign-off to reliably unleash the full performance potential of advanced technology nodes
2006-10-03 Synopsys triples TetraMAX ATPG speed
Synopsys said enhancements to its TetraMAX ATPG product enable a typical speedup of threefold or more in runtime performance across all design styles compared with the previous version
2004-03-18 Synopsys takes another stab at FPGA synthesis
Synopsys has tweaked its Design Compiler ASIC synthesis tool to enable designers to use the same tools and potentially the same design flow for ASICs and FPGAs
2005-07-22 SMIC and Synopsys announce reference design flow 2.0
Synopsys Inc. and Semiconductor Manufacturing International Corp. (SMIC) said Tuesday (July 19) that they have developed a new RTL-to-GDSII reference flow based on Synopsys' Galaxy design platform and SMIC's 130nm process
2005-07-22 SMIC and Synopsys announce reference design flow 2.0
Synopsys and SMIC said they have developed a new RTL-to-GDSII reference flow based on Synopsys' Galaxy design platform and SMIC's 130nm process
2002-08-29 Prolific joins Synopsys in-Sync, TAP-in programs
Prolific Inc. has joined the Synopsys in-Sync and TAP-in programs to ensure interoperability of its ProLiquid software with Synopsys' PrimeTime and Library Compiler tools, and the Liberty modeling format.
2003-04-25 PrimeTime tool steps up to 50 million gates
A new release of Synopsys' PrimeTime tool claims a runtime performance boost of two- to seven-fold over previous releases.
2006-10-19 IC firms collaborate with Synopsys to validate new ATPG tech
Synopsys has collaborated with several semiconductor firms to test a new ATPG technology designed to increase the quality of manufacturing tests by targeting small delay defects
2007-03-09 Fujitsu standardizes on Synopsys solutions for 65nm sign-off
Synopsys Inc. announced that Fujitsu Ltd has standardized on Synopsys' PrimeTime and Star-RCXT products as the timing sign-off solution for its 65nm ASIC and COT design flows.
2004-12-17 Winbond achieves silicon success with Synopsys design platform
Winbond Corp. has achieved first-pass silicon success using Synopsys Inc.'s Galaxy Design platform for its latest 130nm, MPEG-4 multimedia chips
2002-11-05 TSMC adopts Synopsys EDA tools
TSMC has qualified Synopsys Inc.'s signal integrity suite to address the design methodology for its 130nm and 90nm process technologies
2004-05-03 Toshiba used Synopsys platform for SoC designs
Synopsys has announced that Toshiba has taped out multiple 90nm SoC designs for its audiovisual and office equipment product lines using Synopsys' platform
2006-08-30 Toshiba tapeouts 90nm IC with Synopsys compiler
Synopsys announced that Toshiba has used the Synopsys IC Compiler physical implementation solution to tape out its next-generation TC90515XBG home digital network chip
2007-11-09 Synopsys, UMC co-develop 65nm reference flow
Synopsys and UMC have co-developed a 65nm hierarchical, multivoltage RTL-to-GDSII reference design flow
2015-11-11 Synopsys, GlobalFoundries team up for 22nm FD-SOI sol'n
The Synopsys Galaxy Design Platform, enabled for the GlobalFoundries' 22FDX platform, claims to offer FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies
2004-12-03 Synopsys' Galaxy platform supports Sasken reference flow
Synopsys Inc. has announced that Sasken, an embedded telecommunications technology solution provider, has used its' Galaxy design platform to develop a reference flow to enhance the implementation and signoff process for its complex designs
2008-01-29 Synopsys upgrades signal integrity analysis suite
Synopsys has announced that the 2007.12 release of its PrimeTime suite has set a new performance standard for both static timing and signal integrity analysis, accelerating turnaround time and design closure for today's nanometer designs.
2006-10-31 Synopsys unveils DFM tools for 45nm, beyond
Synopsys has unveiled a new family of process-aware DFM products that analyze variability effects at the custom/analog design stage for 45nm and smaller designs
2004-11-23 Synopsys supports Xeon processor with Intel EM64T
Synopsys Inc. claimed to be the first EDA software company to support the Intel Xeon processor with Intel Extended Memory 64 Technology (Intel EM64T) for 64bit and 32bit computing with the Red Hat Enterprise Linux version 3 operating system using its Galaxy design and Discovery verification technology
2005-02-09 Synopsys supports SUSE LINUX with verification platform
Synopsys Inc. will support the SUSE LINUX Enterprise Server 9 operating system (OS) from Novell on both 32bit and 64bit x86 instruction sets for Synopsys' Galaxy Design and Discovery verification platforms
2004-09-03 Synopsys solutions to support IPCore design flow
Synopsys Inc. disclosed that China-based IPCore Technologies Corp. has signed a multi-million dollar agreement
2004-05-24 Synopsys releases design platform upgrade
Synopsys launched an upgrade to its design platform that delivers across-the-board improvements in run-time, capacity, QoR, silicon technology support and turn-around time
2004-11-25 Synopsys offers support to Intel processor with EM64T
Synopsys said it is the first EDA software company to support the Intel Xeon processor with Intel EM64T for 64- and 32bit computing
2004-06-17 Synopsys low-power solution supports 90nm designs
During the DAC 2004, Synopsys announced that its Galaxy Power offers the industry's first comprehensive low-power solution for today's advanced, high-performance 90nm designs
2008-10-03 Synopsys is Sanyo's EDA choice
Sanyo Semiconductor has signed an expanded business agreement to establish Synopsys as its leading EDA supplier
2013-05-08 Synopsys IC compiler update speeds up design closure
The latest release features advanced optimisations to enable high-speed design, efficient implementation of final-stage engineering change orders and tape-out-proven support for FinFET-based processes.
2006-06-30 Synopsys expands test portfolio with NanoTime
Synopsys has announced the availability of NanoTime, a next-generation transistor-level static timing analysis solution
2004-03-31 Synopsys CEO defends MoSys acquisition
Responding to user questions on a variety of topics, Aart de Geus, Synopsys CEO, defended his company's proposed acquisition of MoSys in a new E-Mail Synopsys User's Group (ESNUG) mailing
2009-03-19 Synopsys CEO confident of IC rebound
Synopsys Inc. chairman and CEO Aart de Geus touted the company's new products and said the semiconductor industry would remain critical to the world after emerging from a recession expected to be long and deep
2003-03-25 SMIC adopts Synopsys design platform for silicon processes
Semiconductor Mfg Int. Corp. (SMIC) has selected Synopsys Inc.'s Galaxy Design Platform as the reference flow for its deep submicron processes
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