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2003-03-19 R&D center in China to utilize Synopsys IC design tools
Synopsys Inc. has agreed to donate IC design tools to the High Technology Research and Development Center of the Chinese Ministry of Science and Technology
2009-02-17 Primetime now enables 2x faster runtime
Synopsys Inc. has added a flexible multicore processing technology and new runtime optimizations to the latest release of PrimeTime static timing analysis tool, enabling up to 2x faster runtime, the company said.
2002-06-28 Papers reveal Synopsys, Cadence research projects
Innovation is alive and well as Synopsys Inc. is moving ahead in formal verification, test and synthesis, and Cadence Design Systems Inc. is breaking new ground in timing analysis, asynchronous design and model reduction
2004-04-29 Nvidia GPU designed with Synopsys platform
Synopsys has announced that Nvidia's new GeForce 6800 graphics processing unit was designed with Synopsys' Galaxy Design Platform
2004-10-26 New Synopsys timing model challenges Cadence's ECSM
Seeking a more accurate approach to nanometer delay modeling, Synopsys revealed its composite current source (CCS) model at the Synopsys Interoperability Forum here Thursday (Oct. 21
2005-10-07 New design flow for ARM Cortex-A8 processor from Synopsys
Synopsys and ARM demonstrated the successful integration of Synopsys' Galaxy RTL synthesis, hierarchical design planning, physical implementation solution, sign-off and Discovery verification solution within a high-performance design flow for the new ARM Cortex-A8 processor
2008-07-30 National hails Synopsys as its key EDA partner
Synopsys has announced that the company was chosen by National as its key EDA partner in product development
2008-01-30 Matsushita taps Synopsys compiler for 45nm design
Synopsys announced that its IC Compiler has been used in Matsushita Electric's 45nm SoC device tapeout
2006-10-18 Hua Hong NEC, Synopsys team up for reference design
Synopsys and Hua Hong NEC announced their jointly developed Reference Design Flow 2.0 for Hua Hong NEC's 0.18?m process
2006-04-06 Hisilicon adopts Synopsys' Galaxy design platform
Synopsys announced that Hisilicon Technologies has adopted Synopsys' Galaxy Design Platform as its primary IC design flow for 130nm designs
2005-11-07 DongbuAnam, Synopsys develop 130-nm reference flow
Korean wafer foundry DongbuAnam Semiconductor Inc. and EDA giant Synopsys Inc. have jointly developed a reference flow for DongbuAnam's 130nm process, the companies said Friday (Nov. 4
2005-01-13 Ceva uses Synopsys Galaxy, Discovery for DSP, interface chips
Ceva Inc. has taped out its next-generation high-speed serial interface chips and the CEVA-Teak DSP using Synopsys Inc. Galaxy and Discovery platforms
2015-10-08 ATPG sol'n from Synopsys expedites test pattern generation
The ATPG technology claims to deliver 10X faster run time and 25 per cent fewer test patterns to reduce schedules, speed up silicon debug, and minimise test time and cost.
2015-02-05 ARM, Synopsys join forces for next-gen mobile device designs
The team up will use the IC Compiler II place and route solution to enable superior implementation of power-efficient designs by delivering a reference implementation flow for the ARM Cortex-A72 processor.
2005-02-15 Users laud C design in DAC 'trip report'
Engineers are warming to C language design tools, according to reviews in the Design Automation Conference (DAC) &quote;trip report&quote; released Friday (Feb. 11) by industry gadfly John Cooley.
2004-06-01 Prolific offers tool to assure signal integrity
Prolific announced that the latest version of its timing optimizer works with Synopsys' PrimeTime SI static tool.
2005-05-11 Power network sign-off bridges transistor, gate levels
Claiming a new "hybrid" capability for voltage drop and electromigration sign-off, Synopsys will announce PrimeRail, a combination static and dynamic IC analysis tool that spans the transistor and gate levels
2014-10-02 IEEE board approves OCV extensions to Liberty
The additions pushed forth by Synopsys give designers a modelling technique that may further cut timing margins for advanced process nodes such as FinFET, boosting timing closure turnaround-time
2003-09-12 EDA users call for 64-bit Opteron support
A number of EDA users would like to run 64-bit apps on AMD Opteron servers, but are frustrated by the lack of EDA vendor support.
2003-12-19 Designers stand up for gate-level simulation
In theory, static timing analysis and formal verification should render gate-level simulation unnecessary. But in reality, it's unavoidable, according to a number of engineers who contributed postings to the latest E-Mail Synopsys Users Group (ESNUG) bulletin
2001-05-01 Cadence's 'all-in-one' tool gets skeptic reviews
Cadence's Integration Ensemble (IE) is the first single tool that can take a hierarchical chip design all the way from synthesizable RTL code through a GDSII layout file and designers are raising an eyebrow if it will perform as well as it promises.
2005-03-30 'Concurrent' IC design suite rolls
Synopsys rolled out IC Compiler, which concurrently runs physical synthesis, clock tree synthesis, placement, routing, yield optimization and signoff correlation
2004-05-03 Speakers challenge APIs for EDA interoperability
A standard API and database implementation may not be the best approach to EDA tool interoperability, according to Synopsys speakers at the Electronic Design Processes (EDP-2004) workshop here Monday (April 26, 2004
2011-02-03 Implementation platform addresses Gigascale design
Synopsys Inc. releases the 2010.12 Galaxy Implementation Platform that addresses the scalability, convergence and throughput needs of gigascale IC design
2010-05-17 IC compiler enables faster design closure
Synopsys offers the IC Compiler 2010.03, a physical implementation solution delivering up to 2.5x faster performance on multicorner/multimode designs, and enhanced in-design technology for faster design closure
2006-07-01 Tool suite handles design complexity
Altera Corp. recently launched its Quartus 6.0 tool suite, which includes a timing analyzer that's said to pave the way for next-generation 65nm FPGAs.
2005-06-07 Three tout more nimble physical design
Three tool vendors are pitching breakthroughs in IC physical design in advance of next week's Design Automation Conference
2003-03-07 Silicon Metrics adds signal integrity tool
Silicon Metrics has added to its library development suite a new tool that performs signal integrity noise characterization.
2001-05-16 Sequence Design offers tool for timing closure
Sequence Design has combined different technologies in a "design closure" product that can optimize timing and signal integrity concurrently before and after routing.
2005-02-01 Magma reveals next-gen IC design suite
Magma Design Automation introduced Cobra, an internal development effort that promises a number of technology breakthroughs.
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