Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > Synopsys PrimeTime

Synopsys PrimeTime Search results

?
?
total search77 articles
2003-06-18 EDA startup claims power management breakthrough
Claiming to reduce ASIC power consumption by as much as 25 percent, EDA startup Golden Gate Technology launched the GoPower ofering, which is said to be the first toolset to provide a complete solution for low-power layout.
2006-07-01 DFM tool targets parametric yield
Blaze DFM Inc. recently rolled out Blaze MO, said to be the first "electrical" DFM solution.
2005-04-01 Cobra strikes to reshape IC design flow
Magma Design rolls out its restructured Cobra technology that promises to reshape the nanometer-IC design flow process.
2003-03-20 Circuit Semantics offers noise characterization
Circuit Semantics has announced the availability of the DynaCell-SI, a characterization and modeling solution for signal integrity verification.
2004-04-29 Bad signals interfere with 90nm designs
Bad signals interfere with 90nm designs.
2002-12-27 ACAD fields hybrid power analyzer
Combining gate-level dynamic analysis with static or "semi-dynamic" transistor-level analysis, the company is rolling its Power tool that is capable of checking IR drops for SoC designs.
2006-09-07 'Signoff quality' timing tool rolls for 65/45nm designs
Cadence Design Systems introduced the Encounter Timing System, described as a "signoff-quality" timing product for nanometer SoC design.
2008-06-05 TSMC stirs IC designs using 40nm node
Paving the way for next-generation chips, TSMC is set to roll out its latest design methodology for IC production at the 40nm node.
2004-04-23 Timing optimization rolls for logic designers
Silicon Dimensions has released an add-on to its Chip2Nite floor planner, block design and analysis offering.
2005-04-01 Statistical tool shift: It's all in the timing
Startup Extreme DA's mission is 'variation-aware' IC analysis. Can four guys in borrowed office space make a big impact on chip design?
2004-06-15 Statistical timing can boost IC performance, panelists say
The performance of just about every digital IC design relies heavily on static timing analysis results.
2013-01-25 Reduce power estimation time from weeks to hours
Find out how to automatically generate a chip design's gate-level waveform from the RTL design environment without having to bring up the gate-level environment.
2006-10-16 One timing tool serves 65nm, 45nm designs
Cadence Design Systems introduced the Encounter Timing System, described as a "signoff-quality" timing product for nanometer SoC design.
2007-07-16 Multicore reshapes EDA landscape
The largest EDA vendors acknowledge that the advent of multicore processors is a cause for both celebration and concern. Multicore platforms will provide much-needed compute power as transistor counts soar at 65nm and below. But legacy applications could prove difficult or even impossible to parallelize.
2003-07-14 LG runs ACAD FinePower for digital TV SoCs
LG Electronics has selected ACAD Corp.'s FinePower Dynamic Power tool for the design and verification of complex ICs used in digital TV receivers.
2013-10-04 Lessons learned from TSMC's rise
Herb Reiter shares his personal dealings with TSMC and gives his insight on the valuable lessons he learned from the company's rise.
2004-09-21 Cadence listens to users, CTO says
Cadence Design Systems Inc. is making progress toward addressing new problems popping up in "deep nanometer" IC design and is listening more closely to customer requests.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top