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2004-11-09 Verisity, TransEDA unite respective verification solutions
Verisity Ltd, a supplier of verification process automation (VPA) solutions, and TransEDA, a provider of ready-to-use verification solutions, have jointly announced the integration between vManager and VN-Cover.
2004-03-25 Verisity adds accelerators, emulators to Axis line
Verisity Ltd plans to add dynamically programmable processors to the XoC, Xtreme, and Xcite acceleration and emulation products it acquired in the deal last month for Axis Systems Inc.
2013-06-24 VeriSilicon's ZSP981 core tweaked for advanced wireless tech
The first core in the ZSP G4 series, the is ZSP981 a fully synthesisable, 6-issue superscalar DSP core that runs at 1.2GHz.
2015-04-27 Verilog-AMS vs SPICE view for SoC verification
In this article, we comparatively analyse the usage of Verilog/Verilog-AMS and SPICE views from the perspective of data converters and clocking IPs in an SoC.
2002-03-13 Vendors join push for assertion standards
The strongest effort yet to forge a standard assertion language for IC verification will unfold at the International HDL Conference this week, as Co-Design Automation and Real Intent announce the donation of the Superlog Design Assertion Subset to the Accellera standards body.
2015-03-26 Understanding design compilation in hardware emulators
Design capacity in hardware emulators, also the compilation flow, is heavily dependent on the type of technology utilised in the verification engine.
2012-10-11 TSMC releases 20nm, CoWoS design reference
The silicon-validated CoWoS Reference Flow enables multi-die integration to support high bandwidth, low power and can achieve fast time-to-market for 3D IC designs.
2005-07-01 Truth in advertising
Signal-processing applications are becoming more complicated and more variedand so is the hardware that runs them.
2002-07-24 TranSwitch draws metro processing, switching plans
TranSwitch Corp. has developed a consistent four-element road map that brings together Onex Communications Corp.'s Omni switching and processor architecture.
2002-09-16 Toshiba, Neolinear formulate new methodology for Soc design
Toshiba and Neolinear teams up to implement a new AMS design methodology that enables significant analog design reuse.
2005-08-16 Tool gets a handle on voltage changes
As a chip designer for Intel Corp., Srikanth Jadcherla spent a lot of time working on multivoltage designs. Now he's launched an EDA startup, ArchPro Design Automation Inc., which is rolling out what it presents as the industry's first multivoltage RTL simulation product.
2007-01-10 Tool claims breakthrough in ASIC debugging
Claiming a breakthrough in ASIC debugging, Synplicity will release details about TotalRecall, which it says will bring full debug visibility to FPGA prototypes used for ASIC verification.
2005-08-01 Tool buffs up regression testing
AVS provides a browser interface that serves as a control panel for the verification process where jobs can be launched, suspended or terminated.
2003-06-25 TI starter kits provide low-cost DSP designs
Texas Instruments has announced the availability of two low-cost DSP starter kits for the TMS320C64x and the TMS320C67x devices.
2005-09-06 TI expands Aureus DSP family
Texas Instruments introduced the next generation in its Aureus family of audio DSPs for applications requiring multi-channel decoding.
2004-05-13 Tharas spins new accelerator box
Tharas' new version of its hardware accelerator compiles Verilog, VHDL or mixed-language designs at rates of 20 to 50 million register-transfer-level equivalent gates per hour.
2014-10-22 Test setup for 5G generates, analyses signals up to 67GHz
The test setup consists of the up to 20GHz R&S SMW200A high-end vector signal generator, a harmonic mixer from subsidiary Radiometer Physics and the R&S FSW67 high-end signal and spectrum analyser.
2005-06-27 Tektronix acquires test software supplier
Test and instrumentation company Tektronix Inc. has acquired TDA Systems, a supplier of interconnect analysis software tools.
2007-03-16 Take distinctive approach to IC verification
Richard Goering spoke with Hooman Moshar about Broadcom's distinctive approach to IC verification.
2005-02-28 Synopsys' HSPICE MOS model supports Oki LCD TV driver SoC
Synopsys and Oki Electric disclosed that Oki has standardized on the new HSPICE high-voltage MOS model for the design of Oki's LCD TV driver SoC.
2005-06-08 Synopsys enhances DesignWare with SATA addition
Synopsys Inc. has added Serial ATA (SATA) verification intellectual property (VIP) to its DesignWare Library
2005-10-27 Survey finds verification tool use largely unchanged from 2004
The 2005
2004-04-21 Startup's tool adds hardware validation
Carbon Design Systems has expanded the capabilities of its DesignPlayer models to perform hardware validation as well as presilicon software validation.
2004-02-05 Startup to speed co-verification
A small EDA startup based in Eindhoven, Netherlands, has big plans to speed up hardware/software co-verification.
2011-12-12 Sony CTO details next-gen chip requirements
Sony's Masaaki Tsuruta detailed at the International Electron Devices Meeting the requirements needed for next-generation gaming chips.
2002-11-18 SoC/IP designs need next-gen solutions for integration verification
As the cost of SoC design plus time-to-wolume pressure continue to rise, a next-generation simulator for SoC integration verification is required to ensure functionality.
2011-06-08 Simulation tool offers Xilinx FPGA verification
MathWorks announced the availability of its EDA Simulator Link 3.3 with new FPGA-in-the-loop capabilities for Xilinx FPGA development boards to help engineers verify their designs at hardware speeds.
2002-05-23 Rival RF design flows get a boost
Two former software partners will square off at the Design Automation Conference next month with their respective RF IC design and simulation tools.
2005-03-01 RF ICs: Moore's Law on steroids
After a long period of dormancy, Moore's Law is taking hold of the wireless chip market.
2005-08-01 RF IC tools still seeking paths to silicon
Complicated by multiple modulation schemes, RF tools have become proficient at simulating behavior on an architectural level.
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