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2002-03-07 Reversible computing could pinpoint network congestion
A Rensselaer Polytechnic Institute researcher has proposed a method for network modeling that he claims could significantly cut the time required to locate points of congestion.
2007-02-01 Retired industry pioneer muses on IC trends
Epitaxy innovator and SIA founder Wilf Corrigan shares with EE Times his take on the developments in semiconductor business.
2015-09-16 Resolving giga-scale challenges in memory design
Advanced designs are more complex and larger than ever before, and designers are balancing between accuracy and performance for large scale memory simulation and verification.
2015-06-11 Realising true FPGA-based verification
The scale of the latest FPGA technology is making that valuable emulator speed-up possible, but without the capital and operating expense associated with the big-box.
2011-09-22 Real-time testing, HIL tools cut test dev't time
The NI VeriStand 2011 expands deterministic test execution with looping and branching structures and multitasking.
2006-09-18 Re-thinking SoC design at 65nm, below
Executives from major IC houses and EDA companies have been talking about the design challenges facing developers as SoC designs move from 65- to 45- and 32nm.
2009-02-19 Rapid prototyping & core vs. context
For many companies, the answer is that prototype design has become context and the smart move is to work with a trusted partner for prototype development, enabling key engineering and management talent to engage on core activities.
2011-12-15 Prototyping: Virtual vs physical
Simulating and analyzing the products in software during the design process provides significant time-to-market and quality advantages over older practices of producing multiple physical prototypes and testing them in the lab.
2006-03-16 Primitive tools slow analog/digital integration
With the right tools, the job of integrating high-performance A/D circuits on the same SoC could be easier.
2007-05-17 Platforms upgrade custom IC, PCB design
Cadence Design Systems claims to have a "complete" custom IC simulation and verification solution, along with an advanced constraint-driven PCB design flow with announcing the release 6.2 of its Virtuoso MMSIM tool.
2011-11-03 Perform assertion-based verification in mixed-signal design
Understand how assertion-based verification can address the challenges in analog/mixed-signal verification.
2004-03-16 Passive integration activates wireless
The PiiP concept is a unique design approach for integrating package-level design into the silicon world via BiCMOS SiGe process.
2009-08-28 Parallel programming keeps up with multicore boom
Researchers have been at work for a little over a year with grants from Intel and Microsoft, forming ideas about the future of chips with dozens or hundreds of cores and coding prototype parallel software to harness them.
2006-04-27 PA manages to boost standard, EDR Bluetooth signals
SiGe Semiconductor has extended its RangeCharger IC product line with the SE2425U power amplifier for Bluetooth.
2011-10-24 Overcome challenges of ASIC/SoC prototyping with FPGAs
Learn about FPGA-based prototyping and the various factors that must be taken into account to successfully implement a prototyping strategy.
2006-10-16 Open-source tools ease C++ verification
Two engineers published a book on IC verification with C++ and launched a website with free open-source tools that can help IC verification teams.
2007-09-25 New Genesys software offers enhanced RF statistical capability
Agilent announced it is shipping the latest version of the Genesys software, which includes new statistical and electromagnetic analyses that provide first-pass accuracy for RF and microwave designs.
2007-09-25 National establishes brand for energy-efficient ICs
National Semiconductor Corp. announced that its line of energy-efficient, high-performance power and analog signal-path products will carry the PowerWise brand.
2007-07-16 Multivoltage verification solution eases low-power design
MaVeric is a comprehensive multivoltage verification solution that hopes to ease designers' struggles with low-power designs that require the verification of multiple voltage "islands."
2010-04-30 Multicore DSPs enable code, tool reuse
Freescale has released a family of programmable DSPs that delivers the optimal blend of low cost and high performance for medical, aerospace/defense and test/measurement markets.
2015-01-26 Microbial programming underscores high market potential
Intel, Microsoft and Autodesk are playing catch-up to Microbial Robotics, which has perfected its ViruBots and BactoBots based on programming living organisms to perform humanitarian tasks.
2005-05-02 Micrel releases SPICE models for MOSFET driver ICs
Micrel Inc. announced the immediate availability of a suite of SPICE models for its MIC44xx family of low side MOSFET driver ICs.
2008-04-16 Manage circuit board power with PLDs
This article proposes a design solution to the complex power management problem in circuit board design: the use of a programmable, mixed-signal power management device.
2003-03-17 Low-power design can bring down product cost
EDA and design communities have often focused on the high-end market driven by networking equipment without considering power; this focus must change as the economics of low-power design will drive a new segment of the ASIC market.
2010-04-07 Low-cost GPS/Galileo test set runs 3D simulations
Aeroflex has launched a lightweight, easy to use, configurable and inexpensive portable GPS and Galileo positional simulator that creates 3D simulations.
2013-01-23 Lattice upgrades FPGA design software
The company debuted the latest versions of Lattice Diamond and iCEcube2 design tools that claim to improve power calculations and design productivity.
2004-04-07 Keithley to distribute Elgar power supplies in Asia
Keithley Instruments Inc. has signed an agreement with Elgar Electronics Corp. to sell, service, and support the full line of Elgar programmable power supplies through Keithley's sales and support offices located throughout China, Taiwan, and Japan.
2004-08-02 Is verification really 70 percent?
The oft-quoted statistic that functional verification takes 70 percent of the chip design cycle may be more myth than science.
2013-06-21 Intel expands Xeon Phi range
Intel's Xeon Phi coprocessor families offer something for every supercomputer user, from high-end systems to workstations to embedded systems.
2000-12-01 Infiniband requires design trade-offs
Primary players in the computer industry are developing the Infiniband architecture as the next generation of server I/O, with the intent of eventually replacing PCI.
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