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total search169 articles
2007-02-01 Cadence deploys CPF in low-power design flow
Cadence Design Systems has added the Common Power Format (CPF) to its existing logic design, verification and implementation tools.
2005-02-01 Bluespec synthesizes SystemVerilog verification assertions
The startup has announced its ability to synthesize SystemVerilog verification assertions into Verilog 1995 RTL code.
2005-01-31 Back to the language roots
Although SystemC has its place in the hardware-design process, it still can't compete with Verilog and VHDL.
2007-09-12 AWR fields non-gridded EMF solver software
AWR is launching an electromagnetic analysis tool called Axiem that it claims offers a sufficient speed up to allow EMF solving to be used in design rather than a post-design check.
2006-04-13 Audio DSPs target low-cost home, automotive apps
Texas Instruments has launched the latest versions of its Aureus generation of audio DSPs.
2004-01-01 Assertion flow debuts
The Assertion Studio allows users to mix and match assertions if needed to add verification IP to their designs.
2001-06-01 ASIC generation revamped for IP reuse
For designers, the linchpin for complete IP reusability is the programmable VLIW processor core, along with programmable buses and interface ports.
2008-03-20 Ansoft tips Nexxim v4, Designer v4
Ansoft has released new versions of Nexxim, the company's high-capacity circuit simulation software, and Ansoft Designer, its integrated schematic and design management software.
2008-05-16 Analog tools require reinvention
Until recently, the majority of ICs were either purely digital or purely analog in nature. Today, to satisfy cost, size, weight and power consumption requirements, sophisticated combinations of analog and digital functions are being implemented on "mixed-signal" devices.
2006-04-18 Aldec solution increases network-based design verification
Aldec's new mixed-language solution promises to dramatically increase network-based design verification.
2002-06-14 Aldec extends RTL hardware accelerator capacity
Aldec Inc. has announced the availability of the Riviera IPT v12000 functional RTL hardware accelerator that handles up to 12 million FPGA gates.
2003-07-28 Agilent taps startup's Verilog-A compiler
Adding behavioral modeling to its analog design tool suites, Agilent announced an agreement to integrate Verilog-A modeling technology from Tiburon-DA.
2011-09-29 Agilent discusses Asia business, modular instruments
In conversation with EE Times-Asia, Lawrence Liu, Agilent's regional manager, talks about their measurement forum, Asian business and modular instrument strategy.
2015-08-26 Agile techniques for hardware design (Part 2)
In Part 2 of this Agile Hardware article, we will reveal the actual costs, and discuss the implications for Agile hardware development.
2011-08-01 Addressing signal integrity issues in high-speed flash devices
Learn what can affect signal integrity and how to model and measure it.
2003-06-10 Accellera launches new verification standards
Accellera announced that its Board and Technical Committee members have approved four new standards for language-based design verification.
2008-08-20 3D EM simulation solution rolls for RF module design
Agilent Technologies Inc. has developed the EMDS-for-ADS, an integrated design flow solution that includes full 3D electromagnetic (EM) simulation for RF Module Design.
2010-06-23 24-core DSP delivers over 36 GMACs at <55mW
Boosting the processing power of its DSP chips, Octasic Inc. is increasing the number of Opus DSP cores from 15 to 24.
2003-11-13 0-In assertion compiler has multilingual features
The company will announce an enhanced assertion compiler for its Assertion-Based Verification (ABV) tool suite.
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