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What is an embedded system?
An embedded system refers to any electronic system that uses a CPU chip, but that is not a general-purpose workstation, desktop or laptop computer. Embedded systems generally use microprocessors, or sometimes custom-designed chips or both. It is used in various applications such as vehicles, machine tools and consumer electronics.
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2006-06-15 Cadence offers 'first' transaction-based system verification
Cadence unveils 'first' automated end-to-end transaction-based system verification and management solution.
2006-08-11 Cadence introduces line of reusable verification IP
Cadence Design Systems recently introduced the Universal Verification Components (UVCs), a new line of reusable verification IP (VIP).
2005-06-15 Cadence details enterprise verification strategy
Cadence Design Systems Inc. outlined the company's strategy for "enterprise" verification process automation (VPA) at a breakfast for journalists and analysts Monday (June 13) kicking off the Design Automation Conference (DAC).
2005-10-20 Cadence backs IEEE P1647 e standardization
Responding to user demand for a standard verification language, Cadence Design System, Inc. announced their support for the IEEE P1647 e standardization effort. Cadence also contributed resources for technical editing and program management to ensure the standard is of the highest quality and completed on time.
2004-01-14 C-based co-development environment rolls for FPGAs
Startup Impulse Accelerated Technologies Inc. has rolled out its CoDeveloper product, which offers a hardware/software co-development environment for FPGAs.
2009-10-05 Braving software-to-silicon verification challenges at 45nm
Software-to-silicon verification holds immense challenges at 45nm and beyond for system designers and tool vendors, with multiple paradigm shifts converging at the same time.
2005-06-15 Bellum Software debuts tool for capturing comms protocols
Protocollum allows designers to set up much of their system through point-and-click operations
2004-12-01 Behavioral synthesis rebounds in marketplace
Y Explorations enhances its synthesis tool to work from untimed ANSI C-language input.
2004-06-01 Behavioral synthesis crossroad
Ten years after its market entry as the next generation in synthesis, Synopsys' Behavioral Compiler is dead. Can somebody else breathe new life into behavioral synthesis?
2007-04-16 AzureIP library accelerates ESL synthesis
Claiming to set a new direction for silicon intellectual-property (IP) design and reuse, Bluespec Inc. has rolled out the AzureIP Foundation Library, a set of parameterized IP blocks for use with the company's Bluespec Compiler.
2005-03-08 Atmel, Celoxica co-develop ESL design for latest processors
Atmel Corp. and Celoxica Ltd have cooperated to extend electronic system level (ESL) design to a family of dynamically reconfigurable processors currently under development at Atmel.
2006-01-18 Asynchronous EDA tools coming in Q2, says Silistix
Silistix, a spin-out company from an asynchronous logic research group at the University of Manchester in England, has announced further details of its asynchronous interconnect design tools.
2012-06-01 ASTC, Tanner to partner in ASIC design
John S. Zuk, vice president for marketing & business strategy at Tanner EDA, specified that ASTC teams will be utilizing the complete Tanner EDA tool suite.
2001-06-01 ASIC generation revamped for IP reuse
For designers, the linchpin for complete IP reusability is the programmable VLIW processor core, along with programmable buses and interface ports.
2003-03-07 ARM, Cadence ink five-year design chain optimization deal
ARM will provide direct access to ARM intellectual property to facilitate optimization of design and verification solutions from Cadence's design and verification solutions on ARM core-based SoCs.
2003-03-10 ARM expands training program to Germany
ARM Ltd has announced that Doulos Central Europe is now part of the ARM Approved Training Center Program, extending the ARM program to Hannover, Germany.
2006-03-31 Aldec offers 90-day free access to Riviera Verilog simulator
Aldec announced full simulation support in Riviera for the open-source UltraSPARC T1 from Sun Microsystems.
2006-10-17 Aldec claims Verilog simulation speedup
Aldec's new Riviera-Pro 2006.10 HDL simulator promises to provide a 57 percent speedup for RTL simulation and a 250 percent speedup for gate-level and timing simulations over previous releases of the software.
2015-08-26 Agile techniques for hardware design (Part 2)
In Part 2 of this Agile Hardware article, we will reveal the actual costs, and discuss the implications for Agile hardware development.
2008-09-02 Achieve efficiencies with algorithmic synthesis
Algorithmic synthesis moves the creation of application engines (algorithms on silicon) to a higher level of abstraction, giving significant time and cost savings.
2011-06-23 Accellera, OSCI team up unifies EDA standards
Accellera and OSCI are joining forces to create a single organization, a move that will accelerate development of system-level standards as well as chip design and verification standards.
2013-04-04 Accellera launches EDA, IP interoperability standardisation
The company formed a multi-language working group to create a standard and functional reference for interoperability of multi-language verification environments and components.
2008-01-21 'Open' is (not) just a four-letter word
There is presently a measure of "openness fatigue" permeating the industry, but that's because the term "open" has been far too often applied to products and organizations that are far from open in significant ways.
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