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| 2012-10-30 | KALRAY completes 256-core SoC using Mentor's sol'ns The KALRAY MPPA-256 manycore processor is a 256-core SoC with 47MB memory using Mentor's functional verification, physical design and verification, and design-for-test flow product suites. |
| 2016-01-05 | Enhance test quality, minimise DFT costs Learn about two test solutions that can be implemented to exploit additional advantages of hybrid silicon test solution. |
| 2013-09-11 | Mentor, ASSET tout IJTAG chip-to-system-level IP integration Mentor revealed full interoperability between the Tessent IJTAG chip-level IP integration product and ASSET InterTech's ScanWorks platform for embedded instruments. |
| 2010-11-04 | Mentor Graphics, ARM team up for memory test Mentor's Tessent memory test and repair solution now supports ARM's memory BIST bus and interface that provides external access to all memories contained within the processor core. |
| 2012-10-17 | TSMC names EDA partners for CoWoS, 20nm TSMC has validated technologies from Cadence, Mentor and ANSYS for use in its 20nm and CoWoS design infrastructure. |
| 2011-09-21 | Reference flow eases ARM CPU testing ARM and Mentor have developed a test flow for ARM processor-based designs. |
| 2011-06-07 | Mentor, Samsung develop net-based critical area analysis Mentor and Samsung developed a design automation that significantly improves understanding of design and manufacturing interactions on net-based CAA resulting to improved IC yield. |
| 2010-01-14 | Freescale taps Mentor test, verification tech The collaboration enables Freescale's deployment of Mentor's technologies to enhance design flows and methods. |
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