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2006-11-03 Test challenges could trump future chip designs
Coming silicon process generations will bring not only immense increases in device density, but also the challenges of working with process and device variations that in many ways are worse than for the processes of 20 years ago.
2006-10-30 ITC panel debates on cost-of-quality
Assessments of the total cost of quality need to take into account reliability, delivery, adherence to requirements, and the quality of the user experience, according to an executive panel at the ITC.
2007-10-30 Intel exec calls for advanced test tools for next-gen SoC
In his talk at the opening of last week's International Test Conference, Gadi Singer, Intel Corp. VP and assistant general manager, stressed the need to improve test development tools for next-generation SoC.
2001-06-16 EDA Consortium tackles FPGA productivity
The recent EDA Consortium tackled important issues that focus on direct HDL entry and better productivity measurements for designers and engineers.
2001-05-16 C++ backed for system-level design
The industry must solve the problems of a synthesizable and verifiable C++ subset that has extensibility despite language constraints and lack of transportable libraries.
2001-10-01 Attending to signal integrity in complex designs
This technical design article focuses on the signal integrity tools required to enhance the facilitation of IC design and processing.
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