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2005-03-31 Structured ASICs walk a fine line
A company must make sure that its wares are not too general-purpose to offer attractive performance and that it isn't launching too many specific products.
2008-01-24 Stratix III FPGA features 340K logic elements
Altera says it has developed the industry's highest-density FPGA, the EP3SL340, which features 340,000 logic elements.
2009-04-29 Startup Cswitch battles IC downturn
After making a big splash in 2006, configurable chip startup Cswitch Corp. is going through rough waters amid the IC downturn.
2013-01-08 Start-up takes FPGA design to the cloud
Plunify boasts that its multiple servers accelerate design flow and the cloud provides secure design collaboration capabilities.
2014-12-18 Software speeds up design with Arria 10 FPGAs, SoCs
Altera's Quartus II software v14.1 enables users to quickly design and deploy solutions geared for computationally intensive applications such as high-performance computing, radar and medical imaging.
2011-12-15 Software promises speedier FPGA design
The Lattice Diamond design software targets high volume, cost- and power-sensitive applications.
2005-10-11 Software offers graph-based physical synthesis into FPGAs
Synplicity has expanded its Synplify family of FPGA synthesis tools with Synplify Premier software.
2002-03-19 SiS chipset supports 400MHz DDR memory
Silicon Integrated Systems claims bragging rights with its introduction of what it called the first chipset able to support 400MHz DDR DRAMs.
2004-05-14 Silicon modeling in the nanometer era
With 90nm in production and 65nm on the horizon, designs face increasing challenges: finer line widths, longer interconnect, more routing layers and more analog content.
2006-05-10 SGI adopts Synopsys' topographical tech
Synopsys announced that Silicon Graphics has deployed Synopsys' Design Compiler topographical technology for its next-generation ASIC designs.
2014-06-03 SCI collaborates with Plunify, Optic2Connect for IC design
The SCI Cloud functions as a secure data repository for IC design, manufacturing data, and data provenance. It is geared towards establishing a security model for IC ecosystem providers and users.
2004-11-16 Schulz of Si2 gets jazzed on standards
Steven Schulz's ear for finding harmony amid a cacophony of industry voices may have come from his love of jazz.
2003-04-28 Samsung considers embedding FPGAs in ASICs
Samsung Electronics' semiconductor division said it may embed FPGA blocks in future ASICs as a way to reduce the time and cost of chip design, Samsung Semiconductor Inc. said.
2008-05-09 Run practical power network synthesis
Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes. The method described in this article avoids this unrealistic assumption and introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools.
2002-06-05 RTL-to-GDSII flow shows signs of maturity
The RTL-to-GDSII design flow will take center stage at next week's Design Automation Conference in New Orleans, as several vendors show new technologies intended to solidify an all-in-one flow.
2006-12-21 RTL synthesis tool speeds up run-time
Cadence Design Systems has released Encounter RTL Compiler version 6.2, which promises a 10 percent improvement in quality of silicon and a 30 to 50 percent run-time speedup.
2011-11-14 RTL sol'n yields ultra low-power design
The RTL Power Model predicts IC power behavior at the RTL level with consideration for how the design is physically implemented.
2014-10-10 Rising costs drive chip companies to alternate routes
The low cost of capital is fuelling M&A across all industries, and the rising cost and complexity of making chips is pouring gas on the fire in semiconductors.
2002-04-15 Researchers propose dual design verification model
Indian researchers are proposing a novel verification methodology that uses two representations of a design throughout the verification process, one a behavioral model in C and the other an RTL model.
2005-06-29 Renesas tapes out 90nm production using Synopsys Galaxy
Renesas Technology Corp. has taped out a 90nm SoC design for wireless applications using Synopsys Inc.'s Galaxy design platform.
2006-06-16 Reining in IC power requires careful plan
Michael Burstein of Golden Gate Technology discusses tips on addressing power consumption as an integral part of any design methodology.
2013-07-30 Reduce SoC power use without high-level EDA tools
Read about several situations where high level design tools are not useful and are sometimes a hindrance.
2014-12-09 Reduce power SoC consumption in the interconnect
Here's a modular approach to SoC interconnect for reducing power consumption. The modular concept is different because it consists of a distributed architecture of various components.
2006-08-18 Realtek, Cadence collaborate on formal verification design
Cadence Design and Realtek Semiconductor announced that they have collaborated to successfully reduce the risk of functional errors on its pilot multi-supply voltage design.
2004-05-17 QuickLogic FPGAs supported by Magma synthesis tool
QuickLogic has announced that Palace, the Magma physical synthesis tool for programmable logic devices, now supports its mWatt Eclipse II and Eclipse FPGA products.
2008-11-05 Quartus II software version 8.1 rolls
Altera have unveiled their Quartus II software version 8.1 for CPLD, FPGA, and HardCopy ASIC designs.
2007-10-05 Quartus II FPGA design software version 7.2 debuts
Altera has released its Quartus II FPGA design software suite version 7.2 that includes productivity and performance-focused enhancements that enable designers to achieve faster compile times and meet performance requirements.
2006-07-07 Power reduction tool from Azuro extends to 65nm
Azuro has released version 3 of its PowerCentric low power clock implementation tool, which extends the company's power reduction capabilities to support advanced variability-aware design flows at 65nm and below.
2004-05-20 PMC-Sierra debuts integrated SoC
PMC-Sierra is debuting a CPU-based offering that looks a lot more like an application-specific standard product than like a traditional CPU.
2013-05-23 Performing synthesis-aware clock analysis
Read about a tool that performs clock structure analysis by tracing complex clock nets and visually presenting them to designers.
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