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2007-04-02 Synopsys design platforms support UPF 1.0
Synopsys Inc. has announced a low-power design flow that will implement the Accellera Unified Power Format version 1.0 in its IC verification and implementation products in the second half of 2007.
2008-01-24 EDA trio offers UPF-based products
Magma Design Automation, Mentor Graphics and Synopsys are now delivering low-power EDA tools based on the Accellera-developed Unified Power Format standard, UPF 1.0.
2009-02-13 What's in store for P1801 (Unified Power Format)?
A common industry standard for low power design and verification will satisfy what customers have needed all along.
2007-06-18 The intricate dance of cutting power consumption
Key players in the industry are collaborating to deliver low-power solutions that bring more automated EDA tools, smarter IP, standard formats and more power-stingy processes together into true end-to-end solutions. EDA and IP companies have worked within the Accellera standards organization to develop the Unified Power Format (UPF).
2013-12-03 RTL signoff: A design imperative
"RTL Signoff" as an established concept has gained significance in the last year. However, writes Atrenta's Piyush Sancheti, does a commonly accepted definition of RTL signoff exist?
2007-03-16 CPF-compliant tools aim for low power
Cadence Design Systems Inc. has added the Common Power Format to its existing logic design, verification and implementation tools.
2007-02-01 Cadence deploys CPF in low-power design flow
Cadence Design Systems has added the Common Power Format (CPF) to its existing logic design, verification and implementation tools.
2008-11-03 A less visible, yet important, ballot is underway: P1801
In The Standards Game, there is another important ballot underway: IEEE P1801, formally known as the "Standard for Design and Verification of Low Power Integrated Circuits".
2007-03-27 The dilemma of two languages in low-power design
EDA users may not like it, but when it comes to low-power design they will probably have to speak two languages: CPF and UPF.
2012-08-08 Grasping power awareness in RTL design analysis
Find out how formats such as CPF and UPF play a key role in capturing power intent for RTL design analysis and verification.
2015-11-23 What makes hardware emulation so compelling
Here is a quick assessment of the evolution of hardware emulators over the past two decades, comparing where things stood in the 90s to where they are today.
2012-04-20 Verification platform geared for SoC, FPGA design
Mentor Graphics' Questa 10.1 release claims to increase productivity with regard to verification and boasts enhanced support of the Universal Verification Methodology.
2008-06-16 UMC tips roadmap, veers away from 450mm
Taiwan foundry United Microelectronics Corp. has outlined its process roadmap and disclosed several alliances with the EDA community at the Design Automation Conference (DAC).
2008-06-05 TSMC stirs IC designs using 40nm node
Paving the way for next-generation chips, TSMC is set to roll out its latest design methodology for IC production at the 40nm node.
2014-11-20 The ways to verify SoC
In this article, we will start with the discussion on what and why of verification and only then consider the how.
2013-08-15 Tabula's stylus compiler adds SystemVerilog support
Verific's software serves as the front end to a wide range of EDA and field programmable gate array tools for analysis, simulation, verification, synthesis, emulation and test of RTL designs.
2015-11-11 Synopsys, GlobalFoundries team up for 22nm FD-SOI sol'n
The Synopsys Galaxy Design Platform, enabled for the GlobalFoundries' 22FDX platform, claims to offer FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies.
2014-06-06 Synopsys joins in ST-Samsung FD-SOI collaboration
The extension of the collaboration facilitates the provision of Synopsys' Galaxy design flow for ST's 28nm FD-SOI technology, the adoption of which is expected to be accelerated.
2008-02-26 Rhines on EDA: End 'endless verification'
Walden Rhines of Mentor Graphics calls for a combination of formal methods, TLM techniques and intelligent testbenches to lower the cost of design verification.
2013-12-18 Prototyping family optimized for IP, subsystems
Synopsys' FPGA-based HAPS Developer eXpress includes customized synthesis and debug software to speed prototype bring-up and streamline the transition from individual IP blocks to full SoC validation.
2009-07-28 Power to take center stage at DAC
Power, arguably today's No. 1 headache for designers, will be the theme of workshops, tutorials, meetings, presentations and technical tracks at the 46th Design Automation Conference (DAC).
2013-06-10 Power manager for Mindspeed's Comcerto 2000 comms processor
AGGIOS and Mindspeed Technologies released the AGGIOS CLIOS Power Manager that claims to achieve the lowest power states and shortest wake-up times for optimal whole-system power management.
2009-03-19 Power management for optimal design
This article describes a holistic approach for managing and optimizing the power in a design. Effective power management involves proper understanding the application of a chip, technology selection, design techniques and methodology.
2012-06-18 Managing power islands on chips
Read about the use of power-aware emulation to verify the logic-level robustness of an SoC in the face of power changes.
2007-03-05 Magma tools cut clock tree power draw by 25%
Magma Design Automation has introduced a pair of low-power IC implementation and analysis tools that the company claims have been shown to reduce power consumption in nanometer ICs by 25 percent.
2014-09-05 If Moore's Law hangs back, revert to using old nodes
As the cost of scaling below 28nm multiplies, there has been a corresponding push to create new designs at established nodes using everything from near-threshold computing to back biasing and analogue sensors.
2009-03-24 IEEE okays low-power design spec
The IEEE has approved a new standard that provides portability for low-power design specifications that can be used throughout the electronic system design, analysis, verification and implementation flow.
2007-03-23 Hope fades for IC power standards union
The hoped-for-convergence between two rival IC low-power specifications will not likely take place anytime soon.
2007-05-01 Hope dims for power spec merger
Two rival specification formats for low-power IC design are now publicly available, and backers of both agree that it would be technically feasible to converge them into a single standard. But disagreements over how that convergence should take place threaten to block further progress.
2015-02-09 Hardware emulation: The most versatile of them all
Nowadays, one of the most popular verification tools is hardware emulation and it might remain so in the next few years. Here is a look at the reasons behind its eminent success.
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