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2015-05-15 Enhancing analogue design verification using UVM
In this article, we explore an efficient, reusable analogue and mixed-signal verification approach using the Universal Verification Methodology.
2011-05-04 Design software supports UVM
SpringSoft has announced complete support for UVM with its Verdi Automated Debug System that enables UVM code and enhanced transaction-level analysis to ease debug of SystemVerilog testbenches.
2014-12-11 LPDDR4 verification IP speeds up verification sign-off
The LPDDR4 VIP from Synopsys, based on a 100 per cent native SystemVerilog UVM architecture, aims to enable ease of use, integration and performance with regard to high-performance, low-power designs.
2012-09-05 EVE's ZeBu, SystemVerilog used by Fujitsu Kyusyu Network
The ZeBu hardware-assisted verification platform and SystemVerilog methodology are used by the Japanese company to implement UVM co-emulation.
2011-05-13 Software expands verification interoperability
Springsoft's Verdi debug software expands verification interoperability with complete UVM support enabling UVM code and better transaction-level analysis to ease debug of SystemVerilog testbenches.
2012-01-03 Protocol transactors tout faster SoC verification
The Veloce transactors enable the use of stimuli generated by modern simulation test benches including SystemVerilog/OVM and UVM, SystemC and C-based environments
2013-06-21 MIPI-protocol VIP provides exhaustive stress test
Mentor Graphics' MIPI VIP enables the use of stimuli generated by modern simulation testbenches, including SystemVerilog/UVM, and SystemC-based environments.
2013-05-09 Why stitch and ship is no longer workable
As the systems change, the stitch and ship methodology is leading to increased numbers of costly failures.
2015-11-23 What makes hardware emulation so compelling
Here is a quick assessment of the evolution of hardware emulators over the past two decades, comparing where things stood in the 90s to where they are today.
2012-04-20 Verification platform geared for SoC, FPGA design
Mentor Graphics' Questa 10.1 release claims to increase productivity with regard to verification and boasts enhanced support of the Universal Verification Methodology.
2015-05-15 Verification IP for DDR4 3DS allows higher-density DRAMs
Synopsys' VIP for DDR4 3DS is natively integrated with its Verdi protocol analyser, offering a graphical protocol-aware debug environment that synchronises memory transactions with signals.
2016-05-16 The ideal union of PAM and Ethernet
Understand how various Ethernet speeds evolved through the utilisation of various pulse amplitude modulation (PAM) schemes.
2014-03-07 Synopsys unveils verification compiler sol'n
The Verification Compiler is a portfolio of integrated, next-generation verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure.
2011-02-09 Synopsis launches verification migration program
Synopsys has launched its verification FastForward migration program and invited Cadence Incisive and Mentor Questa users to join.
2015-01-23 Streamline embedded designs with virtual platforms
The virtual prototype kits from Mentor are intended for automotive in-vehicle infotainment, ECU networks, medical and industrial, networking, and military and aerospace product development.
2015-06-11 Realising true FPGA-based verification
The scale of the latest FPGA technology is making that valuable emulator speed-up possible, but without the capital and operating expense associated with the big-box.
2015-06-24 PCIe IP with system-level data protection targets cloud apps
The DesignWare Controller IP for PCIe 4.0 supports multiple lanes/datapath widths for optimal configurations, as well as Native, ARM AMBA AXI-3 and AMBA AXI-4 interfaces for easy integration into SoCs.
2012-08-30 Overcoming challenges for SoC verification team
Know the unique problems that SoC verification engineers face and the approach that provides them a level of automation similar to that enjoyed by block-level verification teams.
2013-10-11 Mentor verification solutions target HDMI 2.0 products
Using the Mentor verification solutions, designers can test the HDMI 2.0 devices, and develop and stress-test their software and hardware with billions of verification cycles before silicon is available.
2015-01-22 Memory VIP speeds up mobile design verification closure
The added features of Synopsys' verification IP portfolio will enable project teams using the JEDEC UFS, MIPI UniPro and JEDEC eMMC protocols to expedite verification closure of mobile and SoC designs.
2012-07-19 Exploring innovations in hardware debug
Searching few new ways to inject quality into a design is where the focus should be in hardware development, not in improving debug tools and techniques.
2016-01-04 Examining memory models
Know the qualities you should look for in memory models, and learn about a library touted to deliver the most comprehensive solution of this kind and supports any type of simulation environment.
2013-05-27 EnSilica, Cross Border Tech target Asian, EU markets
EnSilica partnered with Cross Border Technologies to accelerate the sales of both its IC design services and system IP solutions particularly in Germany, France, Japan and Korea.
2014-04-09 Emulation tech charts path to mainstream adoption
Now faster, easier, and cost-effective, the hardware emulation market's prospects look positivewith annual revenues estimated to climb $1 billion by 2017.
2012-10-10 Developing reset-aware OVM testbench
Learn about each verification component and the changes required in consideration of the reset conditions.
2012-05-17 Design suites hasten system integration
Cadence's SDS and Verification IP Catalog have been expanded to give engineers the ability to go beyond simulation to speed verification of large-scale SoCs, subsystems and systems.
2016-05-02 Data inspection techniques for massive memory designs
Learn about efficient data inspection techniques that will help you reduce the verification stint in a large storage high bandwidth DDR-based memory design.
2014-12-04 Calypto intros high-level synthesis tech to speed up design
The Catapult 8 with the configurable hierarchical design architecture is built on a completely revised architecture that expedites design and verification closure, pushing widespread adoption of HLS.
2014-01-15 Cadence unveils Incisive 13.2 for SoC verification
The Incisive 13.2 platform from Cadence Design Systems offers features two new engines and additional automation features to speed SoC verification closure.
2013-09-10 Cadence rolls out verification IP for HDMI 2.0
The VIP allows designers to quickly and thoroughly verify that their SoCs conform to the HDMI 2.0 specification, accelerating ramp-up to mass production.
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