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2004-06-01 Adveda launches extension to RTL simulator
Adveda introduced its Univers Modeler, an extension to its RTL simulator, which generates a SystemC wrapper or a PLI/FMI wrapper around a native simulation model
2003-03-05 Cadence verification platform has unified methodology
Cadence Design Systems Inc. has launched its Incisive verification platform that supports a unified verification methodology for the embedded software, control, data path, and analog/mixed-signal/RF design domains
2004-10-22 Cadence to add assertion library to platform
Cadence said it will add new assertion-based verification functionality and a new ABV library to its Incisive verification platform's Unified Simulator.
2004-10-21 Cadence to add assertion library to platform
Cadence Design Systems Inc. said it will add new assertion-based verification (ABV) functionality and a new ABV library to its Incisive verification platform's Unified Simulator.
2002-08-01 Endeavor delivers co-simulation solution for Virtex-II Pro
Endeavor Intertech Corp.'s CoSimple hardware/software co-simulating solution targets Xilinx's Virtex-II Pro FPGAs with the IBM PowerPC 405 processor core.
2008-03-26 Xilinx design tools suit logic, embedded, DSP
Xilinx has introduced its ISE Design Suite 10.1, a single unified release providing FPGA logic, embedded and DSP designers with immediate access to the company's entire line of design tools with full interoperability
2002-09-16 Unifying software, hardware design environment
Using a unified design environment can help resolve the simulation problems encountered when incorporating new design trends into existing ones
2014-09-25 Synopsys platform speeds up time-to-market for advanced SoCs
The Synopsys Verification Continuum introduces Unified Compile with VCS and Unified Debug with Verdi across the verification flow, speeding time-to-market by months for complex SoC designs
2005-04-21 AWR signal-integrity suite links ICs, packages, PCBs
Claiming to provide a "unified platform" for signal integrity analysis at the chip, package, module and PCB levels, Applied Wave Research is rolling out the AWR SI 2005 design suite, an extension of the company's existing RF design tools
2013-01-25 Reduce power estimation time from weeks to hours
Find out how to automatically generate a chip design's gate-level waveform from the RTL design environment without having to bring up the gate-level environment.
2004-12-30 ABV solution speeds verification of complex designs
Cadence announced a comprehensive assertion-based verification solution as a part of its Incisive functional verification platform.
2007-06-01 XA offers better simulation accuracy
Promising a new approach to fast Spice simulation, Synopsys Inc. introduced Discovery AMS 2007, a group of solutions that includes the XA simulation technology option for the NanoSim and HSim fast SPICE simulators.
2008-02-18 Why we need a new analog design flow
Analog-mixed signal designers need a first-time right design methodology now. Why is this familiar cry more urgent and probably truest this time?
2008-06-12 TSMC targets to unify 32nm design flow
Facing the 32nm challenge, Taiwan Semiconductor Manufacturing Co. Ltd is putting the pedal to the metal with a new design-for-manufacturing scheme.
2007-02-21 SystemVerilog falls short for design
SystemVerilog is widely applied to verification, however, design use lags due to concerns about tool support.
2004-01-30 Synopsys acquires ADA for analog boost
Making further inroads into the analog design market, Synopsys on Wednesday (Jan. 28) announced its intention to acquire the assets of Analog Design Automation for an undisclosed sum.
2002-09-18 Sugar language sweetens assertions
Three EDA vendors will announce support for the Sugar 2.0 formal property language, adding to a growing list of endorsements that suggests this new Accellera standard will be widely accepted.
2006-09-18 Spice tools rev speed, accuracy
Berkeley Design Automation released in August two products that claim to speed Spice simulation by five- to tenfold while preserving full Spice accuracy.
2010-12-06 SMIC chooses Cadence for 65-nm reference flow
Cadence Design Systems, Inc., has just announced that SMIC has adopted Cadence Silicon Realization products for the DFM and low-power technology at the center of SMIC's 65-nanometer Reference Flow 4.1.
2012-10-29 SliceKIT officially enters XMOS into the board market
XMOS' sliceKIT consists of a core board powered by a 16-core xCORE multi-core microcontroller and equipped with four expansion slots that can be populated with I/O extension cards.
2008-10-09 PolyCore MCAPI offers ThreadX RTOS support
Express Logic and PolyCore Software have announced the first commercial RTOS integration of the Multicore Association's recently released Multicore Communications API (MCAPI) specification.
2010-08-10 Platform tapes out 180nm CMOS bus controller
Synopsys reports the tape out of a complex mixed-signal chip using the company's Galaxy Implementation Platform, including full-chip editing and final chip-finishing tasks.
2011-11-03 Perform assertion-based verification in mixed-signal design
Understand how assertion-based verification can address the challenges in analog/mixed-signal verification.
2004-03-16 Passive integration activates wireless
The PiiP concept is a unique design approach for integrating package-level design into the silicon world via BiCMOS SiGe process.
2007-07-16 Multivoltage verification solution eases low-power design
MaVeric is a comprehensive multivoltage verification solution that hopes to ease designers' struggles with low-power designs that require the verification of multiple voltage "islands."
2007-07-02 Modern IDEs redefine 'integrated'
Multicore processors help embedded designers achieve higher system integration with new IDEs that enable the development of real-time and human-directed portions of an application within tools.
2012-05-24 Low-power DSP architecture meets wide range of wireless standards
The CEVA-XC4000 programmable low-power DSP architecture framework uses an innovative instruction set to enable highly complex, software-based baseband processing which otherwise could only be accomplished with dedicated hardware.
2014-06-23 Engineers handpick 10 best free analysis, design tools
The list includes what is considered a viable alternative to Excel, the R Project, and mathematical tools such as Sage and GNU Octave.
2014-05-30 DSP processors notch up low power consumption
The Synopsys processors implements a three-stage Harvard architecture pipeline that provides efficient throughput, delivering up to 1.77DMIPS/MHz while consuming only 7?W/MHz in the 40nm LP process.
2010-12-13 Cadence, SMIC collaborate for 54nm SoC flow
Semiconductor Manufacturing International Corp. has adopted Cadence's Encounter Digital Implementation System as the foundation for SMIC's Reference Flow 4.1.
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