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| 2003-12-10 | Software yields graphical 'views' from HDL code Novas Software Inc. will announce the Reusner Design Knowledge Publisher, which generates and automatically updates graphical "views" from HDL code. The views can be used for debugging or documentation. |
| 2003-03-03 | Novas adds assertion support to debugger Novas Software Inc. has added OpenVera assertion support to its new Verdi Behavior-Based Debug System. |
| 2014-05-29 | Breker gains Synopsys' VIA membership The membership will facilitate the integration of its TrekSoC software to generate self-verifying C test cases to run on embedded processors with Verdi, allowing users to move seamlessly between TrekSoC's GUI and the Verdi environment. |
| 2015-05-15 | Verification IP for DDR4 3DS allows higher-density DRAMs Synopsys' VIP for DDR4 3DS is natively integrated with its Verdi protocol analyser, offering a graphical protocol-aware debug environment that synchronises memory transactions with signals. |
| 2014-09-25 | Synopsys platform speeds up time-to-market for advanced SoCs The Synopsys Verification Continuum introduces Unified Compile with VCS and Unified Debug with Verdi across the verification flow, speeding time-to-market by months for complex SoC designs. |
| 2011-05-13 | Software expands verification interoperability Springsoft's Verdi debug software expands verification interoperability with complete UVM support enabling UVM code and better transaction-level analysis to ease debug of SystemVerilog testbenches. |
| 2011-05-04 | Design software supports UVM SpringSoft has announced complete support for UVM with its Verdi Automated Debug System that enables UVM code and enhanced transaction-level analysis to ease debug of SystemVerilog testbenches. |
| 2014-03-07 | Synopsys unveils verification compiler sol'n The Verification Compiler is a portfolio of integrated, next-generation verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure. |
| 2015-03-13 | Synopsys bares infringement-free ZeBu server emulators Due to a court injunction prohibiting them from marketing emulators that incorporate Mentor Graphics-patented emulation technology, Synopsys released infringement-free versions of ZeBu emulators. |
| 2008-04-04 | Springsoft, Novas ink merger agreement Springsoft Inc. and Novas Software Inc. have signed an agreement for Springsoft to acquire all the outstanding shares of Novas that it does not already own. |
| 2008-07-16 | SpringSoft works on global ambition In its thrust to offer additional specialized EDA solutions, SpringSoft has completed its merger with Nova Software, and has announced the acquisition of four EDA and channel companies. |
| 2011-03-08 | SpringSoft software offers reusable behavior analysis database SpringSoft's Siloti Visibility Automation System claims a streamlined, easy-to-use flow for SoC verification and debug that speeds up design preparation time by at least 10X over previous releases. |
| 2013-01-25 | Reduce power estimation time from weeks to hours Find out how to automatically generate a chip design's gate-level waveform from the RTL design environment without having to bring up the gate-level environment. |
| 2008-01-02 | Presenting an EDA success story The success of SpringSoft Inc. the leading EDA player in the Asia-Pacific, demonstrates a very special and precious story. Martin Lu, chairman and CEO, attributes their success to two important factors: right product positioning and the realization of a designer-centered concept. |
| 2006-05-01 | Novas tool lets designer see data from debugging This new type of tool set should help IC designers gain visibility into the signal values they really want to see. |
| 2015-01-22 | Memory VIP speeds up mobile design verification closure The added features of Synopsys' verification IP portfolio will enable project teams using the JEDEC UFS, MIPI UniPro and JEDEC eMMC protocols to expedite verification closure of mobile and SoC designs. |
| 2014-12-11 | LPDDR4 verification IP speeds up verification sign-off The LPDDR4 VIP from Synopsys, based on a 100 per cent native SystemVerilog UVM architecture, aims to enable ease of use, integration and performance with regard to high-performance, low-power designs. |
| 2011-10-05 | Debug platform eases SoC design, verification SpringSoft's open platform allows the creation and sharing of custom applications through the company's debug system. |
| 2005-01-31 | Back to the language roots Although SystemC has its place in the hardware-design process, it still can't compete with Verilog and VHDL. |
| 2015-10-08 | ATPG sol'n from Synopsys expedites test pattern generation The ATPG technology claims to deliver 10X faster run time and 25 per cent fewer test patterns to reduce schedules, speed up silicon debug, and minimise test time and cost. |
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