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2009-02-06 Virtex-5 Embedded Tri-Mode Ethernet MAC hardware demonstration platform
This application note describes a system using the Virtex-5 Embedded Tri-Mode Ethernet MAC wrapper core on a Xilinx Virtex-5 ML505 or ML507development board.
2007-01-26 Virtex-4-based devt platform speeds embedded system designs
Xilinx has announced immediate availability of the Pb-free, RoHS-compliant ML410 development platform based on the Virtex-4 FX60 FPGA.
2006-03-31 Virtex-4 FPGAs turn into traffic managers for triple-play apps
Xilinx has partnered with Modelware to provide designers of networking infrastructure equipment with a product that will enable them to integrate advanced traffic management features into their systems.
2005-03-31 Virtex-4 FPGAs boast lower power
Xilinx raised the performance benchmark again by claiming that v4.1 of its Web Power Tool provides 1W to 5W lower power per FPGA in its Virtex-4 family.
2000-06-23 Virtex synthesizable high-performance SDRAM controller
This application note describes the design and implementation of a synthesizable, parameterizable, flexible, auto-placed-and-routed synchronous DRAM controller in the Virtex FPGA family.
2001-04-12 Virtex series configuration architecture user guide
This application note presents an overview of the Virtex series architecture by emphasizing data bit location in the configuration bit stream.
2000-06-21 Virtex power estimator user guide
This application note explains how to use the Power Estimator worksheet, which is used to calculate estimated power consumption for Virtex designs. This worksheet considers the design resource usage, toggle rates, I/O power, and many other factors in the estimation.
2000-06-21 Using the Virtex SelectIO
This application note describes how to utilize the highly configurable, high-performance SelectIO I/O resources of the Virtex FPGA series to provide support for a wide variety of I/O standards.
2000-06-26 Using the Virtex delay-locked loop
This application note demonstrates how to use the Virtex FPGA Series' four fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits to implement several circuits that improve and simplify system-level design.
2000-06-23 Using the Virtex Block SelectRAM+
This application note demonstrates how to utilize the Virtex FPGA Series' dedicated blocks of on-chip 4.096kb dual-port synchronous RAM by using each port of the block SelectRAM+ memory independently as a read/write, read or write port, and configure each port to a specific data width.
2008-02-21 Tensilica processors support Virtex-4 LX200 dev't kit
Tensilica has added support for Avnet's Xilinx Virtex-4 LX200 development kit for high-speed hardware-based simulations to its Xtensa configurable and Diamond Standard processor families.
2007-03-12 Synthesizable CIO DDR RLDRAM II controller for Virtex-4 FPGAs
This application note describes how to use a Virtex-4 device to interface to Common I/O (CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices. The reference design targets two CIO DDR RLDRAM II devices at a clock rate of 200/235MHz with data transfers at 400/470Mbps per pin.
2008-05-22 Storage solution designed for Virtex-5 FPGAs
Xilinx has announced a flash-based configuration and storage solution for the Virtex-5 family that delivers new levels of configuration performance for meeting today's high-speed connectivity requirements.
2002-06-28 SONET rate conversion in Virtex-II Pro devices
This application note targets Virtex-II Pro designs that require the direct use of Rocket I/O transceivers in 16-bit mode.
2006-10-11 Soft processor delivers 50MFLOPS for Virtex-5 FPGAs
Xilinx has released version 5.00 of the MicroBlaze soft processor that extends floating point performance of 65nm Virtex-5 FPGAs to 50MFLOPS, a 50 percent improvement over previous versions.
2009-06-05 SEU strategies for Virtex-5 devices
Xilinx devices are designed to have an inherently low susceptibility to single event upsets (SEUs). This application note provides a substantial discussion of strategies and representative calculations for handling SEUs with an emphasis on reliability when addressing these low probability events.
2006-04-03 Serial RapidIO IP core available for Virtex, Spartan FPGAs
Mercury announced the availability of a new Mercury Serial RapidIO IP core for Xilinx Virtex (high-performance) and Spartan FPGA families.
2006-04-14 Serial IO toolkit simplifies debug of Virtex-4 FX RocketIO transceivers
Xilinx's Serial IO toolkit is designed to reduce the cost and complexity of debugging high-speed serial IO designs.
2008-02-28 S2C equips Virtex logic module with USB-enabled runtime control
S2C has released its third-generation rapid SoC prototyping tool, the Dual Virtex-5 TAI Logic Module equipped with two Xilinx LX series Virtex-5 FPGAs, which supplies up to 6.6 million ASIC gates of capacity.
2008-08-29 RTOS support rolls for PowerPC 440 core on Virtex-5 FPGA
The folks at Express Logic, supplier of royalty-free RTOS, and Avnet Electronics Marketingsay that the ThreadX RTOS now supports the PowerPC 440 processor embedded in Xilinx Virtex-5 FPGAs.
2004-12-10 RocketIO X transceiver clock mode switcher for Virtex-II Pro X FPGAs
This app note demonstrates a way to switch clocking modes without knowledge of a PMA attribute bus interface.
2009-01-23 RLDRAM II memory interface for Virtex-5 FPGAs
This application note describes how to use a Virtex-5 device to interface to Common I/O (CIO)
2002-12-26 Reference design supports Virtex-II, CoolRunner-II
Xilinx Inc. has announced that its PicoBlaze 8-bit microcontroller reference design now includes support for the company's Virtex-II series of FPGAs and CoolRunner-II CPLDs, giving customers access to microcontroller solutions that utilize the company's complete range of programmable products.
2004-12-10 QDR II SRAM local clocking interface for Virtex-II Pro devices
This app note discusses a 200MHz four-word burst QDR II SRAM interface implemented in a Virtex-II Pro XC2VP20 FF1152 -6 device.
2009-04-01 QDR II SRAM interface for Virtex-5 devices
This application note describes the implementation and timing details of a Quad Data Rate (QDR II) SRAM interface for Virtex-5 devices.
2007-03-12 PowerPC processor with floating point unit for Virtex-4 FX devices
This application note describes how to implement a Virtex-4 FX PowerPC 405 system with the Xilinx floating point unit (FPU) coprocessor. An FPU connected to the PowerPC auxiliary processor unit (APU) interface can accelerate software applications from anywhere between three to twenty times. The reference design provided includes a completed design created using the Xilinx Embedded Development Kit (EDK). Source code for a finite impulse response (FIR) filter is provided along with a graphics utility for display output on a Windows-based PC.
2008-04-18 PMC modules interface I/O signals to Virtex-5 FPGAs
Acromag's PMC-VSX modules feature a DSP-optimized Xilinx Virtex-5 FPGA that is reconfigurable for high-performance I/O processing and user-developed algorithmic computation.
2007-02-28 PCIe, GbE, XAUI protocol packs roll for Xilinx Virtex-5 FPGAs
Xilinx Inc. has announced the availability of protocol packs for PCIe, GbE and XAUI for its 65nm Virtex-5 family of FPGAs.
2008-05-05 NI adds Virtex-5 FPGA to PXI I/O devices
NI has released four R Series I/O modules for the PXI platform that are equipped with Xilinx Virtex-5 FPGAs: the NI PXI-7841R, PXI-7842R, PXI-7851R and PXI-7852R modules.
2009-02-04 Next-gen Virtex, Spartan FPGAs launched
Xilinx Inc. is simultaneously launching the next generations of its high-end Virtex and low-cost Spartan FPGAs, billed as the foundation for "targeted design platforms" that the company says will be supported by IP cores, design environments, reference designs and scalable boards and kits offered by Xilinx and third-party partners.
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