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2000-06-21 Using three-state enable registers in XLA, XV, and SpartanXL FPGAs
This application note shows how to use hard macros to implement the use of the internal IOB three-state control register, which can significantly improve output enable and disable time, in both HDL- and schematic-based designs.
2001-06-15 Using team design for large FPGAs
This application note describes how to perform team design optimization (such as Virtex) for large FPGAs.
2002-06-28 Using a microprocessor to configure Xilinx FPGAs via slave serial or selectMAP mode
This application note discusses the configuration of Xilinx's Virtex and Spartan FPGAs using a microprocessor via slave serial or selectMAP mode.
2010-12-14 Use RLDRAM II memory interface for FPGA
Learn how to use a Virtex-5 device to interface to Common I/ Double Data Rate Reduced Latency DRAM devices.
2010-12-15 Use QDR II SRAM interface for FPGA
Read about the implementation and timing details of a Quad Data Rate SRAM interface for Virtex-5 devices.
2005-05-10 Two new design tools from Xilinx
Xilinx announced the immediate availability of its System Generator for DSP v7.1 development software and XtremeDSP Virtex-4 SX35 development kit for digital communication system design.
2002-06-28 Two flows for partial reconfiguration: Module based or small bit manipulations
This application note describes the steps required to design, implement, verify and reconfigure the Virtex and Spartan series of FPGAs using module-based and small-bit method of partial reconfiguration.
2005-10-03 Tools figure into designers' platform picks
With latest-generation DSPs well accounted for, chip vendors are turning their attention to beefing up software development tools.
2004-05-13 Tharas spins new accelerator box
Tharas' new version of its hardware accelerator compiles Verilog, VHDL or mixed-language designs at rates of 20 to 50 million register-transfer-level equivalent gates per hour.
2002-12-10 Tarari adopts Xilinx FPGAs
Tarari Inc. has chosen Xilinx Inc.'s reprogrammable chip technology for the development of the Tarari Content Processing Platform.
2000-06-23 Synthesizable 143MHz ZBT SRAM interface
This application note demonstrates a Virtex design that interfaces to megabytes of external high-speed ZBT (Zero Bus Turnaround) SRAM in order to provide interleaved read/write without wasteful turnaround cycles.
2001-04-12 Synthesizable 1.6GBps DDR SDRAM controller
This application note describes a 100MHz synthesizable reference controller design for a 64-bit DDR SDRAM.
2004-09-17 Synplicity upgrades FPGA logic, physical synthesis tools
Synplicity announced the latest version of its FPGA logic synthesis and physical synthesis software solutions.
2006-10-19 Synplicity offers software support to new Xilinx FPGA
The Synplify Pro synthesis software supports Xilinx's recently introduced Virtex-5 LXT FPGA.
2003-06-27 Synplicity debugger supports latest FPGAs
Version 1.2 of Synplicity Inc.'s Identify RTL debugging software features increased functionality and support for the latest field-programmable gate arrays from Actel, Altera and Xilinx.
2004-10-05 Synopsys DC FPGA supports Xilinx FPGAs, software
The Design Compiler FPGA from Synopsys now supports Xilinx's Virtex-4 family of domain optimized FPGAs and ISE 6.3i place and route software.
2000-06-29 Status and control semaphore registers using partial reconfiguration
This application note demonstrates how to lock the LUT SelectRAM to specific locations, determine the corresponding frame of data in the .RBT (Rawbits) file, modify the LUT memory as desired, and re-write this frame into the chip.
2004-12-09 Statistical profiler for embedded IBM PowerPC
This app note explains how to generate statistical profiling information from the IBM PowerPC 405D, which is embedded in some Virtex-II Pro FPGAs.
2004-12-10 Single error correction and double error detection
This app note describes the implementation of an error correction control (ECC) module in a Virtex-II, Virtex-II Pro, or Virtex-4 device.
2006-02-17 Simplify partial reconfiguration for Xilinx's FPGAs
Xilinx announced the latest version of its PlanAhead software, which along with its ISE software, promises to deliver a two speed-grade performance advantage for Xilinx Virtex-4 and Spartan-3 FPGAs over competing offerings.
2010-12-09 SERDES Framer Interface Level 5 for FPGA
Read about the implementation of SERDES Framer Interface Level 5 (SFI-5) in a Virtex-6 XC6VLX240T FPGA.
2007-07-03 Reference System: PLB Tri-Mode Ethernet MAC
This application note describes a reference system illustrating how to build an embedded PowerPC system using the Virtex-4 PLB tri-mode Ethernet media access controller.
2002-10-01 Programmable logic enables powerful SoC solutions
With the ability to embed complete systems on a single FPGA, programmable logic has enabled a new realm of powerful yet very flexible SoC solutions.
2004-12-09 PPC405 lockstep system on ML310
This app note discusses the implementation of a processor lockstep system using embedded PowerPC 405 (PPC405) processors in Xilinx Virtex-II Pro FPGAs, along with Xilinx software tools.
2002-11-08 Potholes mark ASIC-to-FPGA conversion path
Designers should be aware of several "gotcha's" that can impede designs moving from ASICs to FPGAs, said Mike Dini of The Dini Group.
2007-01-19 PMC/XMC module features ruggedized design
Pentek's Model 7141-703 is configured as a ruggedized PMC/XMC module fully compliant with the ANSI/VITA 20 conduction-cooling specification and ANSI/VITA 42 XMC specification.
2004-10-29 PLD war: There can only be one?
Xilinx claims it will get the top spot in the PLD industry with easy victory. But will rival Altera allow it?
2010-12-10 Perform asynchronous oversampling in FPGA
Read about the Virtex-6 FPGA SelectIO technology that can perform 4X asynchronous oversampling at 1.25 Gb/s.
2004-07-28 Pentek VIM-2 module eyes compute-intensive engines
Pentek developed a high-performance, software radio front-end with two 105MHz 14-bit ADCs and two user-configurable Virtex-II Pro FPGAs.
2005-04-06 Pentek rolls new Model 7131 version
Pentek announced a new version of its Model 7131 16-channel multiband digital receiver PMC module that features two 14bit 105MHz A/Ds and four quad digital receivers.
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