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2000-02-22 An Introduction to Active-HDL Sim
The article provides a brief introduction of Active-HDL Sim post-fitting timing simulator and its role in the Warp design process.
2001-03-28 An introduction to active-HDL Sim
This application note provides a brief discussion to the Active-HDL Sim functional simulator. The discussion includes installing/uninstalling the simulator, creating an 1164/VHDL simulation model, the simulation process, and applying stimulus.
2001-03-22 An Introduction to active-HDL FSM
This application note provides an introduction to the Active-HDL FSM (finite state machine) editor, while highlighting key features of the software and illustrating the steps required to create a state machine.
2004-11-18 Magma, Aldec deliver front-to-back FPGA design flow
Magma Design Automation Inc. and Aldec Inc. have completed the design flow interface between active-HDL 6.3 and PALACE version 2.4.
2003-05-26 FPGA toolset adds C synthesis interface
Bringing C language synthesis to FPGA design, Aldec rolled out its Active-HDL v6.1 toolset.
2004-03-15 EDA tools support new Altera CPLD family
Altera has announced that the new MAX II CPLD device family is supported by much of the EDA industry as well as by Altera's own Quartus II design software.
2003-11-07 Aldec, Celoxica offer C-based FPGA design
Providing a mixed HDL and C-based tool suite for FPGA designers, Aldec Inc. and Celoxica Ltd have announced Active-HDL+C.
2006-05-17 Aldec simulators validated for Lattice devices
Aldec announced that Lattice Semiconductor has validated Aldec's Riviera and Active-HDL simulators for use with Lattice devices.
2002-01-10 Aldec rolls out fast, fully automated FPGA design verification tool
Claimed to be the fastest, most fully automated FPGA design verification tool, Active-HDL 5.1 addresses the latest design trends in the EDA industry, the company says.
2002-05-03 Aldec releases verification software for Xilinx devices
Aldec Inc. has announced the release of the Active-HDL 5.1 XE design software designed specifically for use with high-density Xilinx FPGA devices.
2011-12-15 Software promises speedier FPGA design
The Lattice Diamond design software targets high volume, cost- and power-sensitive applications.
2007-05-25 Partnership eases FPGA, PCB design collaboration
To help facilitate collaboration between FPGA and PCB designers, Zuken and Aldec announced a partnership that will make it possible to launch Aldec's FPGA design tools from within Zuken's CR-5000 PCB design environment.
2008-09-12 ispLEVER service pack to enhance designer's creativity
Lattice Semiconductor has released Service Pack 1 for ver 7.1 of its ispLEVER FPGA Design Tool Suite, providing the latest LatticeMico32 embedded open source microprocessor enhancements.
2011-07-07 FPGAs, PCIe IP core pass PCIe 2.0 compliance
Lattice Semiconductor's FPGA and PCIe IP core passed the PCI-SIG PCIe v2.0 compliance and interoperability testing for 1- and 4-lane configurations.
2010-11-10 FPGA design software updated
Lattice Diamond 1.1 extends support to MachXO and MachXO2 product families
2008-08-29 Design tools support new ultralow power CPLDs
Lattice Semiconductor has released the ispLEVER Classic ver 1.2 design tool suites that will support all its SPLD, CPLD and select FPGA families.
2010-07-07 Design software delivers low-power, low-cost FPGAs
The Lattice Diamond FPGA Version 1.0 design software provides as set of tools and a modern user interface to enable designers to more quickly target low power, cost sensitive FPGA applications.
2007-03-14 Co-verification solution rolls for Actel FPGAs
Aldec has announced the release of CoVer, a Windows-based HW/SW co-verification solution for Actel's ARM-based FPGAs.
2006-05-10 Aldec integrates Altera HDL support in simulator
Aldec announced that its simulator now has integrated HDL support from Altera's Quartus II version 6.0 development software environment.
2009-02-26 65nm FPGAs, clock ICs defy downturn
Seeking to grab share in a down market, Lattice has introduced its first 65nm FPGAs in the market and has expanded its family of differential clock distribution ICs. It also announced the availability of 15 new reference designs and a new development kit for its MachXO PLD family.
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