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2006-06-09 Wintegra adds adaptive clock recovery access suite
Wintegra has announced that it has added adaptive clock recovery to its suite of multi-service access support.
2010-06-24 LatticeSC PURESPEED I/O adaptive input logic user's guide
Today's high speed synchronous interfaces pose challenges to the designer in maintaining clock-to-data relationships, managing data-to-data skew and sustaining jitter tolerance
2004-12-24 CML ADM voice codec provides full duplex functions
The CMX649 adaptive delta modulation voice codec from CML provides full duplex codec functions optimized for cost effective, portable, wireless apps
2002-04-18 TDK LIU hits 155.52Mbps
A SONET/SDH LIU from TDK Semiconductor Corp. operates at 155.52 Mbps (STS-3 or STM-1) and provides a synchronized clock that can be used for backplanes running at 311MHz
2005-02-22 K-Micro expands ASIC portfolio
Kawasaki Microelectronics (K-Micro) has expanded its ASIC intellectual property (IP) portfolio with the additions of fast-lock clock and data recovery (CDR) for fiber-to-the-premises (FTTP) applications, 10Gbps Serdes with optional adaptive receive equalization technology for backplane applications, and PCI Express technology for networking, storage, and consumer applications.
2003-06-11 TDK Semiconductor extends Ethernet transceiver line
TDK Semiconductor Corp. announced that it has extended the availability of its 78Q2120 Ethernet transceiver line and customer designs which allows the porting of new semiconductor processes.
2002-06-26 TDK LIUs integrate programmable jitter attenuator
TDK Semiconductor Corp.'s family of single-chip, multichannel DS3/E3/STS-1 LIUs integrates a programmable jitter attenuator that enables the devices to meet E3/T3 jitter standards.
2007-11-07 Optical signals control mechanical structures
While micro- and nanoscale mechanical structures have long been used to sculpt and channel optical signals, from waveguides to resonators, the roles have lately been reversed.
2014-11-27 How to achieve 200-400GE network buffer speeds
Know how a serial chip-to-chip protocol, with 200-400 GE data rates and 4.5 B read/write transactions, can be used to eliminate throughput bottlenecks at the processor/external DDR memory interface.
2014-06-17 Vision-based AI boosts surveillance applications
Cost, performance and power consumption advances are now paving the way for the proliferation of embedded vision into diverse surveillance applications.
2006-04-24 SDI products target broadcast video apps
National Semiconductor introduced six serial digital interface products for professional broadcast video applications.
2002-09-11 Santel chipset achieves optical compensation
Santel Networks Inc. is pushing the chip level integration of optical compensation a notch higher.
2008-04-01 Optical communications migrate to SFP+
Interface chip vendors in growing numbers are tailoring chips to support the migration of datacom and telecom routers and switches to SFP+, the latest pluggable optical module form factor for use in 10Gbit/s Ethernet and 8.5Gbit/s Fibre Channel systems.
2008-11-17 New tech responds to 40nm, 65nm design needs
Fabless ASIC company Open-Silicon has released new technologies to address design issues common to the 40nm and 65nm nodes.
2007-04-02 New tech pares down I/O power draw
Rambus Inc. and a group of leading academics have set a high-water mark in bringing fast chip-to-chip links into the era of low-power design.
2006-09-26 National unveils 2nd-gen PowerWise EMU, APC2 IP pack
National has announced the second-generation PowerWise EMU and APC2 IP package for reducing power consumption in battery-powered handheld consumer products.
2013-06-14 MoSys debuts 100G full-duplex quad retimer
The LineSpeed MSH210 PHY is a 100G device boasts retimer functionality, supporting both receive and transmit functions for full duplex 4x25-28 operation.
2007-04-18 Lattice unrolls GPON BMR reference design
Lattice Semiconductor has released its PURESPEED I/O burst mode receiver (BMR) FPGA reference design for GPONs.
2006-05-17 Intel to stop Giga chip line
Intel will halt future development of optical physical-layer products developed by Giga A/S.
2008-02-11 GDDR5 gears for bandwidth-hungry graphics
The GDDR5 technology is targeted to become the next predominant graphics DRAM standard and is eyed to boost memory bandwidth of graphics applications to a new dimension.
2002-07-11 Flexible transceiver protects backplane investments
A CMOS octal serdes transceiver from Mindspeed Technologies promises to facilitate seamless system upgrades from OC-12 to OC-48 or OC-192 speeds.
2008-08-01 Demodulator provides reliable reception for China viewers
With the rapid growth of digital TV market in China, Micronas GmbH has launched the DRX 398yZ family of digital terrestrial demodulators.
2007-06-28 Build WiMAX base stations, subscriber stations
Designing for WiMAX requires an understanding of the newest MAC and PHY features for fixed WiMAX systems and applications.
2005-01-07 Agere serdes core rolls for 90nm ASICs
Agere Systems is offering a serdes core for 90nm ASIC processes that's appropriate for several serial-interface standards.
2011-11-17 Address challenges in 40G/100G SerDes design, implementation
Read about the various aspects of SerDes design such as transmit/receive portions.
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