Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > advanced packaging

advanced packaging Search results

total search813 articles
2002-01-15 Huayue Microelectronics opens IC packaging firm in Shaoxing
Huayue Microelectronics Co. Ltd has opened an IC packaging firm, Zhejiang Huayue Package Electronics Co. Ltd, located in Shaoxing City, Zhejiang, China
2004-04-01 GEM Services to offer Fairchild MOSFET packaging tech
Fairchild Semiconductor has reached a licensing agreement with GEM Services Inc.
2011-03-10 Flip chip packaging boasts 40% lower cost
STATS ChipPAC releases a flip chip packaging technology, fcCUBE, that boasts high input/output density, high performance and reliability in advanced silicon nodes.
2013-01-28 Fit in large-capacity memory in advanced-node SoCs
Using large-capacity SRAMs can dramatically reduce leakage and deliver higher system performance while keeping mask costs in check.
2011-06-17 FCI, Fujikura team up for IC packaging tech
FlipChip International and Fujikura Ltd are collaborating in innovating advanced semiconductor packaging technology.
2004-03-23 Fairchild to license MOSFET packaging tech to GEM
Fairchild Semiconductor has reached a licensing agreement with GEM Services Inc. under which the company is offering one of its advanced MOSFET packaging technologies as open tooling for the power semiconductor market.
2015-07-03 Examining 3D embedded substrate power packaging
Here is a look at 3D embedded substrate power packaging technologies, which will be increasingly deployed in everything from cell phones to hybrid electric vehicles
2013-08-22 Embedded packaging cuts PoP height by 40
STATS ChipPAC's ultra thin embedded Wafer Level Ball Grid Array (eWLB) technology offers height reduction in the bottom PoP architecture to provide an ultra thin z-height of 0.3mm.
2013-07-10 Dow Corning boards Imec's 3D IC packaging initiative
Dow Corning has teamed up with Imec to advance enabling technologies for 3D IC semiconductor packaging
2005-05-19 Discrete devices sport new packaging platform
Diodes launched its DFN packaging platform with a new line of discrete devices
2012-11-08 Customised lenset array prepped for advanced e-beam tool
Imec has designed and fabricated an electrostatic micro-lens array for KLA-Tencor's Reflective Electron Beam Lithography (REBL) tool.
2009-01-23 ChipMOS drops packaging deal with Spansion
IC packaging and test house ChipMOS Technologies Ltd has issued a notice of breach and notice of intent to terminate a service agreement with Spansion Inc
2009-02-17 Chip packaging houses in red, too
Like the silicon foundries, IC-packaging houses are also seeing red ink
2014-02-13 Ball grid array replaces standard IC packaging
One of the disadvantages of flip-chip BGA packaging is the dissipation of power and data rates on the enclosed product
2006-02-23 ATMI, TEL partner in photoresist packaging system
ATMI Packaging, a provider of high quality materials-handling solutions, unveiled a packaging system designed for direct pressure dispensing of advanced photoresist chemicals.
2009-10-27 Assembly guidelines for MicroFET-6 packaging
This application note focuses on the soldering and back end processing of the MicroFET-6.
2007-09-10 ASE, Mitsui collaborate on HMT packaging tech
ASE and Mitsui have entered into a cross-licensing agreement and technical collaboration for Mitsui's Hybrid Manufacturing Technologies (HMT) packaging technology
2005-05-03 ASE, FCI ink wafer level packaging deal
Advanced Semiconductor Engineering Inc. (ASE) and FlipChip International LLC (FCI) have signed an expanded technology licensing agreement
2002-12-06 ASE rolls out packaging technology for RFICs
Advanced Semiconductor Engineering Inc. has introduced a QFN packaging solution.
2002-08-01 ASAT to provide packaging solutions to Honeywell
ASAT Holdings Ltd will provide packaging and testing solutions for Honeywell's RF/microwave product family
2007-07-19 Amkor, IMEC sign 3D wafer-level packaging pact
Amkor has agreed to develop 3D integration technology with IMEC based on its wafer-level processing techniques.
2002-04-15 Advanced Technology chip resistor has low temperature coefficient
The RC-02 chip resistor from Fenghua Advanced Technology features a temperature coefficient of 100, allowing it to operate over the -550C to 1250C temperature range. It is also suitable for portable electronics applications
2004-03-24 Advanced sockets offer coplanarity within 0.15mm
The 1mm pitch BGA sockets from Advanced Interconnections provide improved hole-to-hole accuracy, and reduced insertion and withdrawal forces
2005-01-04 Advanced MOSFETs boost dc-dc performance
TAEC added eight new single n-channel devices to its SOP Advance MOSFET family to improve the performance of medium-power dc-dc converters.
2012-07-11 Advanced flip chip packaging tech unveiled
STATS ChipPAC's fcCuBE technology features copper column bumps, bond-on-lead (BOL) interconnection and enhanced assembly processes for high volume production.
2005-01-04 Addressing foundry SoC challenges associated with advanced technologies
As process technologies continue to shrink to 90nm and below, new opportunities are presented to designers that allow them to combine the functions of entire systems onto a single piece of silicon.
2012-09-17 A*STAR, Hitachi Chemical team up on 3D IC packaging tech
Hitachi Chemical hopes to leverage IME's advanced 3D IC process capabilities to enhance material technologies that can support the demanding requirements of thin wafer processing
2007-08-21 A $60M funding for TSMC's packaging tech
Capital appropriations totaling $59.8 million will be set aside by Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) for use in establishing 300mm, wafer-level packaging technology
2009-06-25 3M, SUSS MicroTec advance 3D packaging
3M and SUSS MicroTec have teamed up to expand access to 3M Wafer Support System (WSS) equipment for temporary wafer bonding of ultrathin wafers required for 3D packaging
2006-01-25 Flip-Stack packaging supports wirebond-to-flip-chip transition
Amkor announced the Flip-Stack package solution that is specifically designed to support emerging transition from wirebond to flip chip interconnect for high-performance DSPs, ASICs and RF chips.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

Back to Top