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What is Ultra SCSI?
Ultra SCSI is also called "Fast-20". It is an enhancement of SCSI that results in doubling the FAST SCSI data throughput speeds to 20MBps for 8bit and 40MBps for 16bit. It reduces the maximum allowable single-ended SCSI cable length to 1.5m for five to eight addresses and 3m for four or fewer addresses. Maximum allowable differential (HVD) SCSI cable length is 25m. It is defined in the SPI document of the SCSI-3 spec.
Source: Paralan Corp.
total search829 articles
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2011-07-27 12-, 14bit ADC devices deliver 65C250MSPS
TI has unveiled eight dual-channel ADC devices that feature 6dB programmable gain option and SFDR up to 91dBc for high receive sensitivity in 3G/LTE wireless infrastructure.
2008-09-18 1.5GHz FPGAs target ASIC sockets in complex systems
Achronix Semiconductor uses asynchronous circuitry to deliver a 1.5GHz FPGA samples. The startup hopes to use its three-fold lead in data rates to grab ASIC sockets in high-end communications, test and other systems.
2006-08-07 'First' FPGA-based development kit rolls for PXIe
Claiming an industry first, PLDA recently said it is launching the PXIe XpressLite CY2 Development Kit for CompactPCI Express.
2009-01-27 Using the design security feature in Stratix III devices
As FPGAs start to play a role in larger and more critical system components, it is ever more important to protect the designs from unauthorized copying, reverse engineering, and tampering.
2009-01-12 Using DDR3 SDRAM in Stratix III and Stratix IV devices
DDR3 SDRAM is the latest generation of DDR SDRAM technology, with improvements that include lower power consumption, higher data bandwidth, enhanced signal quality with multiple on-die termination (ODT) selection and output driver impedance control.
2009-01-20 QR matrix decomposition
QR matrix decomposition (QRD), sometimes referred to as orthogonal matrix triangularization, is the decomposition of a matrix (A) into an orthogonal matrix (Q) and an upper triangular matrix (R).
2009-02-23 PCB dielectric material selection and fiber weave effect on high-speed channel routing
This application note is for printed circuit board (PCB) designers planning to use the high-speed transceivers available in Stratix II GX and Stratix IV GX devices and addresses two key design topics.
2009-02-24 Optimizing impedance discontinuity caused by surface mount pads for high-speed channel designs
This application note examines the discontinuities from the DC blocking capacitors and SMA connectors in detail, and provides optimization techniques to minimize their adverse effects in the channel.
2009-03-19 Managing Designs with Multiple FPGAs
Managing designs that incorporate multiple FPGAs raises new challenges that are unique compared to designs using only one FPGA. There are several methods for managing multiple FPGAs in a single design, each of which has its pros and cons
2009-01-21 Implementing PLL reconfiguration in Cyclone III devices
PLLs use several divide counters and different voltage-controlled oscillator taps to perform frequency synthesis and phase shifts.
2009-01-16 Implementing OFDM modulation for wireless communications
This application note discusses various implementation schemes for orthogonal frequency division multiplexing (OFDM) modulation and demodulation.
2009-02-12 Implementing Bus LVDS interface in Cyclone III, Stratix III, and Stratix IV devices
This application note describes how to implement BLVDS interface in Cyclone III, Stratix III, and Stratix IV devices for high-performance multipoint application.
2009-01-13 HardCopy II ASIC fitting techniques
This application note describes some possible design considerations and solutions for fitting a Stratix II FPGA design into a HardCopy II ASIC.
2007-03-05 Dual DIMM DDR2 SDRAM memory interface design guidelines
As applications become more demanding, deeper memory is required leading to the need for more than one DIMM memory configuration. This application note focuses on the system implementation of a dual unbuffered DIMM DDR2 SDRAM memory interface, operating at 267MHz/533Mbps.
2009-02-11 DDR3 SDRAM memory interface termination and layout guidelines
DDR3 SDRAM offers features designed to improve signal integrity of increased bus speed.
2009-02-13 Cyclone III configuration interface guidelines with EPCS devices
This application note describes the methods to interface a Cyclone III device to a serial configuration device (EPCS) using Cyclone III I/O voltages of 3.0V and 2.5V.
2009-02-25 An SOPC builder PCI Express design with GUI interface
This application note teaches you how to build an SOPC Builder system that includes a PCI Express MegaCore function and download it to a development board
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