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What is Ultra SCSI?
Ultra SCSI is also called "Fast-20". It is an enhancement of SCSI that results in doubling the FAST SCSI data throughput speeds to 20MBps for 8bit and 40MBps for 16bit. It reduces the maximum allowable single-ended SCSI cable length to 1.5m for five to eight addresses and 3m for four or fewer addresses. Maximum allowable differential (HVD) SCSI cable length is 25m. It is defined in the SPI document of the SCSI-3 spec.
Source: Paralan Corp.
total search829 articles
2010-12-16 Altera buys OTN IP developer
Altera Corp. has acquired Avalon Microelectronics Inc., expanding its portfolio of customizable IP solutions for Optical Transport Network (OTN) applications.
2008-08-06 Altera brings Zilog to court over patent breach
Altera Corp. has filed suit against Zilog Inc. for patent infringement.
2008-09-10 Altera brings SOPC World 2008 to India, China
India and China will be the locations of Altera Corp.'s annual SOPC World conferences in Asia Pacific.
2002-07-17 Altera beefs up PLD software with ASIC flow, pushbutton utilities
Altera Corp. has upgraded its Quartus II PLD design software with new timing-closure capabilities and other features aimed at both novice and expert designers.
2005-01-25 Altera bares industry's 'compelling structured ASIC solution'
Developed as an alternative to the standard cell, Altera's HardCopy II is a non-reprogrammable device seamlessly migrated from a Stratix II FPGA prototype.
2007-05-09 Altera balances features, price point in new Arria GX
With the unveiling of its latest transceiver-based FPGA family, Altera Corp. claims it has succeeded in treading the thin line between feature set and price point.
2007-08-10 Altera Arria GX dev't kit clears PCI SIG compliance tests
Altera Corp. announced that its low-cost Arria GX FPGA Development Kit has passed PCI-SIG's compliance tests.
2006-11-03 Altera appoints new VP for APAC
Altera Corp. announced that David Shen has joined the company as regional vice president and managing director of the Asia Pacific region.
2005-08-02 Altera apologizes to semi analyst for silent treatment
A controversy pitting Altera Corp. against a semiconductor industry analyst came to a head this week when the company issued an apology for refusing to speak with the analyst, who has been critical of the company.
2005-11-17 Altera announces new lightweight serial interconnect protocol
Altera released SerialLite II, a lightweight serial interconnect protocol for chip-to-chip, board-to-board and backplane applications.
2005-01-03 Altera announces 'fastest FPGA qualified for production'
Altera released what it claims as the industry's largest and fastest FPGA qualified for productionthe Stratix II EP2S90 device.
2005-12-07 Altera affirms Q4 guidance
Altera reaffirmed revenue guidance for the fourth quarter, forecasting company revenue would be in the range of $286 million to $297 million.
2014-04-22 Altera adopts fine-pitch copper packaging for Arria FPGAs
TSMC's flip chip ball grid array package technology utilises fine-pitch copper bumps measuring less than 150?m, providing excellent bump joint fatigue life, improved performance in electro-migration current and low stress on the ELK layers.
2005-07-28 Altera adds faster speed grade to Stratix II devices
Altera disclosed that it is offering a new, faster speed grade for the largest two members of its Stratix II familythe EP2S130 and EP2S180 devices.
2006-05-10 Aldec integrates Altera HDL support in simulator
Aldec announced that its simulator now has integrated HDL support from Altera's Quartus II version 6.0 development software environment.
2004-05-25 Accelerated Tech develops RTOS for Altera Nios II
Accelerated Technology has announced RTOS and development tools support for the new Nios II embedded processor family from Altera.
2005-01-10 When bad packages kill good PCBs
How to avoid packaging problems in off-the-shelf ICs and FPGAs, and ASICs.
2005-05-06 Version 5 of Quartus II available
Altera announced that it is shipping v5.0 of its Quartus II design software, featuring the FPGA industry's first incremental compilation feature.
2007-01-09 Verilog simulator offers faster RTL, gate-level simulation
SynaptiCAD has released VeriLogger Extreme, a compiled-code Verilog 2001 simulator, priced at $4,000 on Windows platforms.
2007-01-31 Verification box exceeds 200MHz speeds
Gidel Ltd's Proc_SoC verification box claims to exceed verification speeds of 200MHz, thanks to a direct FPGA-to-FPGA interconnect scheme.
2007-03-05 Uplink desubchannelization for WiMAX
Altera provides building blocks to accelerate the development of a worldwide interoperability for microwave access (WiMAX) compliant base stations. This application note describes a reference design that demonstrates the suitability of the Altera tools and devices for implementing the uplink desubchannelization function.
2005-04-28 TSMC unveils 65nm process, production due December
Foundry chip maker Taiwan Semiconductor Mfg Co. Ltd unveiled its 65nm manufacturing process at its Technology Symposium held in San Jose, California, declaring that first wafers processed with the rules are expected in December.
2006-07-01 Tool suite handles design complexity
Altera Corp. recently launched its Quartus 6.0 tool suite, which includes a timing analyzer that's said to pave the way for next-generation 65nm FPGAs.
2007-03-16 Tap high-speed FPGA transceiver for PHY
The demand for high-speed transceivers is increasing dramatically as systems are required to support higher data bandwidths, and implement a higher degree of functionality and features density.
2000-03-01 Taking new stabs at programmable analog
Programmable logic has some traditional advantages over ASIC design. The gate count of FPGAs approaches that of custom circuits. FPGAs can be programmed?and re-programmed?out in the field, enabling fast time to market. ASICs, in comparison, need careful attention to layout and fabrication technology. It can take anywhere from six weeks to two years (depending on the complexity of the circuit) to get an ASIC working properly.
2003-11-06 Synplicity upgrades RTL prototyping tool
Synplicity Inc. has released a new version of its Certify ASIC RTL prototyping software with enhanced automatic pin multiplier technology, new compilers and mappers, and support for hardware-based FPGA prototyping systems from AMO and EVE.
2003-06-27 Synplicity debugger supports latest FPGAs
Version 1.2 of Synplicity Inc.'s Identify RTL debugging software features increased functionality and support for the latest field-programmable gate arrays from Actel, Altera and Xilinx.
2006-08-03 Summit on multicore SoCs scheduled on ESC-Taiwan
The Multicore SoC Summit at ESC-Taiwan will discuss the challenges in designing multicore SoCs and will highlight technological trends that are expected to make the engineer's work easier.
2013-05-24 Stratix V GX FPGAs added to PCI-SIG integrators list
Altera's Stratix V GX FPGAs successfully passed all PCI-SIG compliance and interoperability tests, completing inclusion for Stratix V on all three generations of the Integrators Lists for PCIe.
2007-03-05 Stratix III power management design guide
This document provides recommendations and guidelines for power management system design in systems featuring Altera Stratix III FPGAs.
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