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2008-02-18 Why we need a new analog design flow
Analog-mixed signal designers need a first-time right design methodology now. Why is this familiar cry more urgent and probably truest this time
2002-09-16 Toshiba, Neolinear formulate new methodology for Soc design
Toshiba and Neolinear teams up to implement a new AMS design methodology that enables significant analog design reuse
2006-10-16 Startups take on analog design automation
Automating analog IC design has proven to be a tough challenge, but two EDA startups are promising to do just that with a new "analog synthesis" technology
2009-09-04 Automating the analog design flow
Complete automation of the analog IC design flow is a concept that has been debated for decades. The EDA community has focused on automating elements of the design process. But why does 100 percent automation evade us stilland, indeed, should it even be the focus?
2001-06-16 Analog, mixed-signal design flow found wanting
Different views cloud the current analog/mixed-signal design flow issue and should stop concentrating on the problem but find a lasting solution for the industry to further prosper.
2008-06-02 Working on India's analog dream
Notes Anand Valavi of Wipro Technologies, " We want to get to the point where people think if they have some state-of-the-art analog work to be done, India is a good place to do it
2004-03-05 Virtuoso unifies mixed-signal, analog flows
Cadence Design Systems' Virtuoso Custom Design Platform is now able to handle analog and digital blocks in the same design flow.
2005-06-13 VIA integrates Sandwork debugging tools into IC design flow
The analog and mixed-signal debugging tools from Sandwork Design Inc. have been incorporated into the IC design flow of Taiwan-based VIA Technologies Inc.
2007-06-28 TSMC, Cadence team on 65nm wireless design flow
Cadence and TSMC have teamed on nanometer wireless design and produced a new TSMC 65nm RF PDK compatible with the new Cadence Virtuoso custom design platform
2004-06-15 Transition to 90nm raising tough design issues
Experts delving into 90nm design and process development explored a crucial question: How will the average design team handle 90nm design
2012-05-18 TowerJazz reference design flow tips Cadence tech for power management
TowerJazz's Reference Flow 2.0 power management analog/mixed-signal reference design flow integrates power management devices with control logic.
2010-08-31 TowerJazz qualifies Magma's mixed-signal design platform
Magma's Titan software and TowerJazz's foundry technology provide mutual customers with a design and manufacturing solution that accelerates the design-to-silicon process and achieves first-time silicon success
2002-10-04 TI India develops ASIC cell design methodology
Engineers at Texas Instruments India have developed a new specification method for driving cell design flow, overcoming the current lack of a set process for specification capture in ASIC cell design methodology
2005-06-07 Three tout more nimble physical design
Three tool vendors are pitching breakthroughs in IC physical design in advance of next week's Design Automation Conference
2011-01-19 TDKs for analog-intensive BCDMOS chip development
Mentor Graphics and Dongbu HiTek jointly release BCDMOS process technologies which facilitate integration of analog functions, adding high value to IC designs targeting demanding applications
2007-11-09 Synopsys, UMC co-develop 65nm reference flow
Synopsys and UMC have co-developed a 65nm hierarchical, multivoltage RTL-to-GDSII reference design flow
2005-06-21 Synopsys backs migration of analog design to OpenAccess
Synopsys Inc. has joined Si2 as a result of the company's increased presence in analog simulation
2003-03-17 STMicro adopts Agilent RF design environment
STMicroelectronics has selected Agilent Technologies' RF design environment (RFDE) for its RF/mixed-signal IC design
2010-11-15 Single design solution works for PL, hardware, software
Design software vendor Altium Ltd will provide its Altium Designer
2003-02-21 Sanyo adopts Neolinear technology for analog circuit sizing
Sanyo Electric Co. Ltd has deployed Neolinear Inc.'s NeoCircuit for automated analog circuit sizing into its mixed-signal design flow.
2006-06-28 Routing solution speeds design to manufacturing
The Cadence Precision Router speeds design and manufacturing convergence for advanced mixed-signal, analog and custom digital designs
2002-05-23 Rival RF design flows get a boost
Two former software partners will square off at the Design Automation Conference next month with their respective RF IC design and simulation tools
2008-08-07 Researchers provide new circuit design option
Indian engineers say they have found a new way to develop behavioral models for analog and mixed-signal circuit designs based on modular architectures that can be reused in future designs
2004-07-01 Pulsic releases layout tool for analog RF design
Pulsic released a layout tool targeted specifically at analog RF designs and has introduced a new version of its Lyric Physical Design Framework
2001-04-15 Process design kits take aim at custom ICs
This technical article describes Cadence Design Systems' process design kits for 0.25?m and 0.18?m process simulations
2011-02-09 Process Design Kit standards elude industry
Disagreements over approaches to PDK standards have indefinitely delayed a solution could enable and speed up new analog and mixed-signal designs in foundries
2007-08-13 Power up: Summit to highlight power-wise design tips
Power use has a cascading effect from the component level to the application level. A keen awareness of power consumption is critical in the design stage
2007-05-17 Platforms upgrade custom IC, PCB design
Cadence Design Systems claims to have a "complete" custom IC simulation and verification solution, along with an advanced constraint-driven PCB design flow with announcing the release 6.2 of its Virtuoso MMSIM tool
2005-01-25 Platform enables designers to anticipate power requirements at start of design cycle
Faraday introduced its PowerSlash IP family and design platform that enables designers to anticipate low power design requirements at the beginning of the design cycle
2011-01-21 PDK and reference flow for 0.18um power management process
Tanner EDA and TowerJazz announce PDK for 0.18um power management process. Kit includes symbol libraries for schematic capture software as well as parameterized layout generators for L-Edit.
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