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2011-02-16 Nanowire processors pack more arithmetic/logic
Touted as the world's first programmable nanoprocessor, the Harvard-Mitre crossbar nanowire arrays performed both operations and memory functions, since the state of nanowire FETs was non-volatile.
2005-03-16 Crossbar logic shrinks to nanoscale
HP designs a crossbar switch that packs the power of a traditional microprocessor logic unit into just a few square microns
2000-06-22 Using the dedicated carry logic in XC4000E
This application note describes the operation of the XC4000E dedicated carry logic, the standard configurations provided for its use, and how these are combined into arithmetic functions and counters.
2015-03-24 Top 5 problems with programmable logic controllers
PLC's duties are crucial for complex processes. However, like most things in life, they can be both advantageous and disadvantageous. Read this article to discover what can possibly go wrong.
2004-09-17 Synplicity upgrades FPGA logic, physical synthesis tools
Synplicity announced the latest version of its FPGA logic synthesis and physical synthesis software solutions
2002-09-02 LSI Logic DSP integrates 48Kwords of memory
LSI Logic Corp. has announced the availability of the LSI403LP configurable DSP that features a total of 48Kwords of on-chip memory, eliminating the need for external memory
2001-03-21 Efficient arithmetic designs with Cypress CPLDs
This application note is intended to provide designers with some insight into efficient means of implementing arithmetic functions in Cypress Semiconductor's CPLDs
2003-02-13 Hitachi technique to improve LSI performance
Hitachi Ltd has announced the development of a circuit technique that they claim is effective in achieving both high-speed performance and low power dissipation in LSIs such as SoC.
2015-09-21 Examining performance in hardware emulators (Part 2)
In the second instalment of this series, we will examine the relationship between emulation system architectures and their performance.
2005-10-03 Build efficient datapath designs
This article proposes RTL coding guidelines and a context-sensitive RTL datapath synthesis for improving design productivity
2002-11-08 Adder and Subtractor Macros Using Lattice Design Tools
This application note discusses how to build Adders and Subtractors using the Lattice Design Tools.
2003-04-23 Verplex tool now checks datapaths
Verplex Systems Inc. has released an add-on to its Conformal Logic Equivalence Checker that allows the tool to verify complex data path circuitry
2003-06-02 Verplex tool now checks data paths
Verplex Systems Inc. released an add-on to its Conformal Logic Equivalence Checker that allows the tool to flatten data path structures without requiring designers to identify boundaries and architectures
2008-06-02 Use system models for better verification
This article describes the system-level to RTL design and verification flow of a commercial graphics processing chip. In this flow, system models were developed to validate the arithmetic computation of video instructions and were then used to verify the RTL implementation using sequential logic equivalence checking.
2003-01-10 Synplicity revamps ASIC synthesis tool
Synplicity Inc. is stepping up the competition against Synopsys, Get2Chip, and Incentia with its latest Synplify ASIC.
2002-10-22 Open-source C compiler targets FPGAs
Seeking to eliminate the need for detailed hardware expertise for FPGA design, a research group at the Los Alamos National Laboratory developed an open-source C compiler for reconfigurable logic
2004-04-15 Omron makes modular PLCs more affordable
Omron has expanded its portfolio of PLCs with the introduction of entry-level CPUs with all the power of a modular PLC system but without the associated cost.
2004-12-27 How can they learn?
Part Rube Goldberg, part Tinker Toys, Jack's retro toys are taught the basics of digital logic and computer programming in an unusual way
2004-06-01 Embedded synthesis enhances high-density FPGA tools
Tools developed specifically for deep submicron programmable devices are emerging, enabling 100,000 gate and greater FPGAs to become mainstream choices.
2004-03-15 AIL adopts SiliconSmart CR for data path libraries
AIL Co. has adopted Magma Design Automation's SiliconSmart CR for characterization and modeling of nanometer data path libraries.
2000-09-01 Ripple-carry adders
This application note shows how the AT6000 architecture is ideally suited for implementing arithmetic operations, such as parallel adders, via a NAND and an XOR available simultaneously in a single cell
2011-08-23 Integer DSP core processes 100 GMACs/s at 1W
Tensilica's integer DSP core, the BBE64, can compute 100 GMACs/s in less than a Watt and can support designs up to more than a million logic gates
2010-09-09 Georgia Tech demos piezotronic transistors for MEMS apps
Transistors harness the piezoelectric effect in zinc-oxide nanowires to transform mechanical motion into a signal that controls logic operations
2014-04-24 Hardened floating point DSP gives FPGAs a boost
Altera is building hardened single-precision floating point DSP blocks into its FPGAs and SoCs, performing up to 1.5TFLOPS in Arria 10 devices and 10TFLOPS in Stratix 10. Adding a layer of hardened multipliers and adders helped eliminate nearly all the logic usage in existing floating point computations
2003-06-05 Altera FPGAs execute FFT operations
New cores from Altera Corp. configure programmable logic to perform floating-point DSP operations, allowing FFT operations to be executed
2012-04-05 UI as the next battlefield in CE (Part 2)
In the next phase of UI adoption, instead of requiring user training, devices with advanced UIs will need to adapt to consumers so they can be used "out of the box".
2006-01-19 Statistics engine liberates processor in IP-based networks
Integrated Device Technology has developed a chip that tracks statistics in IP-based networks, allowing packet processors to focus on other computer-intensive tasks.
2010-11-12 Silicon startups reveal keys to success
A look at the companies that have made it to the EE Times 60 Emerging Startups list over the past six years shows that they all had a clear sales proposition and that CMOS and software remain fundamental to the industry.
2013-07-30 Reduce SoC power use without high-level EDA tools
Read about several situations where high level design tools are not useful and are sometimes a hindrance.
2004-02-03 QuickSilver in reconfigurable platform push
QuickSilver Technology Inc. said it is ready to take on ASICs and FPGAs with a design platform that uses reconfigurable computing principles.
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