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2007-07-16 Verify designs with assertions
When adopting components of assertion-based verification (ABV) into standard production flows, teams run into several challenges. This article gives tips and tricks when dealing with ABV.
2006-10-16 Transaction assertions boost Jeda NSCa suite
Jeda Technologies is adding transaction-level assertion to native SystemC assertion (NSCa), a verification automation tool suite introduced in February.
2006-04-03 SystemC assertions go 'native'
Jeda Technologies shelved its own Jeda verification language in favor of a new tool suite supposedly equipped with the industry's first 'native' SystemC assertion-based verification automation capability.
2002-09-18 Sugar language sweetens assertions
Three EDA vendors will announce support for the Sugar 2.0 formal property language, adding to a growing list of endorsements that suggests this new Accellera standard will be widely accepted.
2007-09-17 Optimal use of assertions in verification
Assertions provide an efficient way of improving overall design cycle productivity by cutting verification time. Here are some tips in the optimal use of assertions in verification.
2005-11-01 Catching errors early with compile-time assertions
Rather than struggle to debug programs, learn how codes can be crafted so that your compiler can catch layout errors
2005-02-01 Bluespec synthesizes SystemVerilog verification assertions
The startup has announced its ability to synthesize SystemVerilog verification assertions into Verilog 1995 RTL code.
2013-09-11 Understanding contract-based programming
Know what contract-based programming is all about, and how it can be used to make software more reliable.
2002-08-01 Where goes system EDA?
The best chance for easing beyond RTL is the new SystemVerilog 3.0 standard, with its support for assertions, C/C++ data types and a high-level "interface" construct.
2011-05-19 Synthesis tool improves functional coverage
NextOp has introduced its BugScope Assertion Synthesis that automatically generates high quality assertions and functional coverage properties in Verilog formats.
2006-10-10 Revised VHDL adds IP encryption capability
Proclaiming a major step forward for the VHDL design language, the Accellera standards organization this week announced it has approved a revised version of the VHDL specification, which features Property Specification Language (PSL) assertions and IP encryption capabilities.
2004-12-01 Methodology sought for assertion-based verification
Silicon IP providers and creators seek guidelines on how to use assertions effectively, aside from the standard protocols.
2015-04-09 Exploring an approach for improving emulation
Emulator debug capacity will not significantly increase in the near future. Instead, an obvious solution is to embed assertions, which can allow emulation to run at very nearly full speed.
2007-06-18 Define your verification plan with SystemVerilog
The adoption of constrained random testbenches, functional coverage and assertions fits seamlessly with embracing SystemVerilog. The value of these technologies is enhanced with an evolution of the verification planning process from simple test plans to VPA-driven verification plans.
2005-05-04 Cadence formal analysis claims ease of use
Cadence Design Systems is introducing this week Incisive Formal Verifier, a tool that aims to make it easy for IC designers verify assertions in RTL code.
2002-08-21 Axis adds assertion checking to emulation/acceleration
Axis Systems Inc. has devised a way to run assertions efficiently on its hardware platforms and thereby speed up assertion checking and, ultimately, the overall verification process.
2004-01-01 Assertion flow debuts
The Assertion Studio allows users to mix and match assertions if needed to add verification IP to their designs.
2004-01-01 0-In assertion compiler is multilingual
0-In Design Automation announced a compiler that reads assertions in multiple formats and outputs synthesizable Verilog.
2002-10-01 'Religious' wars abound
Should resets be synchronous or asynchronous? Should synthesis handle buffer insertion? Should OpenVera assertions be added to System Verilog? All these questions have provoked controversies in recent weeks, the first two in E-Mail Synopsys Users' Group (ESNUG) postings and at our EEdesign site.
2015-05-14 What to ask during code reviews
There are common issues when reviewing code no matter what the size of the company or how mature the development process. Here are 10 questions that can be asked to help find potential bug-ridden areas.
2015-11-23 What makes hardware emulation so compelling
Here is a quick assessment of the evolution of hardware emulators over the past two decades, comparing where things stood in the 90s to where they are today.
2004-03-25 Verisity adds accelerators, emulators to Axis line
Verisity Ltd plans to add dynamically programmable processors to the XoC, Xtreme, and Xcite acceleration and emulation products it acquired in the deal last month for Axis Systems Inc.
2011-05-25 Verification tool quantifies verification progress
OneSpin launched its first comprehensive automatic metric-driven solution that analyzes and measures formal verification progress and quality in register transfer level (RTL) designs.
2009-01-21 Verification tool provides step-by-step approach
OneSpin Solutions has amended its software and packaged it in a way that supports a step-by-step approach for beginners.
2002-07-10 Verification startup wants everyone to go 'formal'
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2002-03-14 Verification gets no respect, panel says
Verification gets no respect, according to participants in a "value of verification" panel at the International HDL Conference.
2006-04-17 Vendors warm to SystemVerilog
Despite Synopsys' skepticism, synthesis vendors appear strongly supportive of a proposed standard SystemVerilog synthesis subset.
2002-03-13 Vendors join push for assertion standards
The strongest effort yet to forge a standard assertion language for IC verification will unfold at the International HDL Conference this week, as Co-Design Automation and Real Intent announce the donation of the Superlog Design Assertion Subset to the Accellera standards body.
2008-06-02 Use system models for better verification
This article describes the system-level to RTL design and verification flow of a commercial graphics processing chip. In this flow, system models were developed to validate the arithmetic computation of video instructions and were then used to verify the RTL implementation using sequential logic equivalence checking.
2003-08-01 Unifying ESL, verification
Richard Goering says that the industry would need ESL and SystemC. But design for verification, with SystemVerilog, is the most obvious next step for most of today's RTL chip designers.
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