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2005-06-21 Trust designs, but verify, say panelists
Successful IC verification cannot be relegated to second fiddle in the design orchestra, according to experts at the Design Automation Conference.
2004-06-02 TransEDA releases new code coverage tools
TransEDA released a new tool for specification coverage and impact analysis, as well as a new "coverability analysis" option to its VN-Cover code coverage tool.
2003-06-05 TransEDA debuts property verification tool
TransEDA has announced a property and assertion capture and validation tool at the 2003 Design Automation Conference.
2004-03-17 Tool pinpoints false paths, steers designers away
FishTail Design Automation is targeting what sounds like a small niche, but the company says the potential benefits of its technology are huge.
2007-01-10 Tool claims breakthrough in ASIC debugging
Claiming a breakthrough in ASIC debugging, Synplicity will release details about TotalRecall, which it says will bring full debug visibility to FPGA prototypes used for ASIC verification.
2010-06-24 Tips on reducing debug efforts
Debug will get your attention one way or another. If you give it attention early in the development cycle, it will reduce the amount of time spent on debug later and in future designs.
2010-05-28 Timing analyzer speeds up multicore designs
XMOS has released the XMOS Timing Analyzer (XTA) that accelerates the design of embedded applications using its family of XCore processor arrays.
2016-05-16 The ideal union of PAM and Ethernet
Understand how various Ethernet speeds evolved through the utilisation of various pulse amplitude modulation (PAM) schemes.
2007-09-20 Taiwan's MediaTek adopts Mentor's formal verification tech
Mentor Graphics announced that Taiwan's MediaTek has selected the 0-In formal verification technology to make it an integral part of its verification flow for their next generation design projects.
2006-01-02 SystemVerilog won't kill 'e' language
Backers of 'e,' which is nearing IEEE standardization, say that rumors of the language's death are exaggerated.
2007-02-21 SystemVerilog falls short for design
SystemVerilog is widely applied to verification, however, design use lags due to concerns about tool support.
2010-05-11 Synthesis tool handles complex design verification
NextOp is bridging design and verification with the introduction of an assertion-based verification solution to automatically generate functional coverage properties from testbench and RTL.
2004-02-02 Synopsys, Cadence give nod to SystemVerilog changes
Enhancements based on feedbacks from vendors and users spotlighting some shortcomings in the current ver 3.1, will be implemented in SystemVerilog 3.1a.
2004-02-19 Synopsys, ARM to write SystemVerilog manual
Seeking to write the book on how to use SystemVerilog for verification, Synopsys Inc. and ARM Ltd. are working together on a SystemVerilog Verification Methodology Manual and hope to have it ready by June.
2005-06-02 Synopsys VCS NTB solution verifies Huawei ASIC designs
Synopsys Inc.'s VCS comprehensive RTL verification solution with Native Testbench (NTB) technology and comprehensive coverage has been adopted by Huawei Technologies for verification of complex broadband ASIC designs
2003-03-03 Synopsys upgrades VCS and Vera
The company has announced upgrades to its VCS 7.0 Verilog simulator and Vera testbench automation tool.
2005-09-30 Synopsys testbench solution increases verification productivity
Synopsys announced Discovery Pioneer-NTB, a new SystemVerilog testbench automation tool that claims to increase verification productivity and improve the quality of complex SoC and IP designs.
2004-04-06 Synopsys forum updates SystemVerilog support
The message at the Synopsys EDA Interoperability Developer's Forum, convening Thursday (April 1, 2004), is clear; SystemVerilog support is growing.
2003-04-15 Synopsys executive predicts end of VHDL
Synopsys' chairman and CEO Aart de Geus predicted that VHDL will go away in 10 years. De Geus made his prediction at the Synopsys Developers Forum in Santa Clara, California.
2006-03-22 Synopsys claims first complete SystemVerilog flow
Synopsys laid claim to being the first EDA vendor to provide a complete SystemVerilog flow, saying the language is now supported throughout its suite of design and verification products.
2004-06-01 Synopsys adds testbench features to VCS
Synopsys announced a new VCS release with added testbench capabilities that includes features derived from the company's Vera products.
2005-10-27 Survey finds verification tool use largely unchanged from 2004
The 2005
2005-09-01 Sub-$200 tools power 'farms' for verification
Stanley Hyduke sees a not-so-distant future for the semiconductor industry in which companies are running thousands of simultaneous simulations to cope with the verification bottleneck.
2013-10-16 Structural, reset faults in SoC designs (Part 1)
Here's a two-part survey of some of the basic structural issues in reset architectures used in advanced nanometre scale SoC designs.
2007-02-01 Streamline body electronics system development with model-based design
Model-based design reduces time-to-market by ensuring throughout the design process that the control system meets requirements, and by enabling hardware validation as it becomes available through hardware-in-the-loop testing.
2006-07-13 Simulator supports Open IP Encryption design flows
Aldec announced that the new version of its Riviera simulation tool supports design flows based on Synplicity's Open IP Encryption Initiative.
2010-11-05 Sidense asks USPTO to check Kilopass patents
The company, a licensor of one-time-programmable fuse-based memory IP, has petitioned the United States Patent and Trademark Office to invalidate one-transistor memory patents granted to Kilopass.
2013-12-03 RTL signoff: A design imperative
"RTL Signoff" as an established concept has gained significance in the last year. However, writes Atrenta's Piyush Sancheti, does a commonly accepted definition of RTL signoff exist?
2008-02-26 Rhines on EDA: End 'endless verification'
Walden Rhines of Mentor Graphics calls for a combination of formal methods, TLM techniques and intelligent testbenches to lower the cost of design verification.
2005-02-18 Rhines draws roadmap for verification
Mentor Graphics Chairman and CEO Walden Rhines provided the DVCon conference here Tuesday (Feb. 15) with a roadmap for achieving progress in the battle for design verification productivity.
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