Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > assertions

assertions Search results

?
?
total search160 articles
2004-05-19 Lighthouse introduces synthesis tools for Verilog test
Promising to reduce testbench development time by up to 80 percent, startup Lighthouse Design Automation Inc. will introduce tools that synthesize Verilog testbenches from high-level specifications.
2006-09-18 Leverage ESL with legacy RTL
Platform-based design lets designers automatically integrate ESL modules with existing RTL IP. John Wilson gives his tips and tricks.
2006-02-01 Language standards from IEEE open choices
Once seen as competitors, SystemC and SystemVerilog languages appear to be settling into largely complementary niches.
2004-06-01 Jasper upgrades verification product
Jasper has announced its JasperGold product that enables what the company calls a "provably correct design" methodology.
2004-05-06 Jasper upgrades verification product
Jasper Design Automation will announce the latest release of its JasperGold product enabling what the company calls a provably correct design methodology.
2004-07-01 Jasper upgrades verification product
The company has announced the latest JasperGold product enabling what Jasper calls a "provably correct design" methodology.
2005-01-17 Inside a hybrid verification model
The combination of languages, tools, IP and methodologies has morphed the traditional ASIC design cycle into a 'hybrid model' process. Learn more.
2014-04-07 Identifying false paths
Early determination of false paths helps guide the implementation tools to the optimum solution faster.
2010-03-22 IC forecasts: What keeps analysts bullish, worried
Although the signs are positive in the chip sector this year, there are still some concerns. Here are 10 reasons to remain bullishand worriedabout 2010.
2005-03-10 IBM EDA tools emerge from Europe's Prosyd project
One year after the launch of the Prosyd collaborative research project between IBM Corp., Infineon Technologies AG and STMicroelectronics NV with about 4 million euros (about $5.3 million) of European tax payers' money, the project has helped IBM produce chip design verification tools.
2004-06-09 Hynix's nonmemory operations selling surfaces
The creditors of Hynix Semiconductor Inc. had announced to withdraw the plan of selling its non-memory operations last April, but it has completely changed a month later.
2008-08-01 FPGAs are all set for next process nodes
Altera Corp. today is expected to become the first FPGA vendor to launch a family of 40nm FPGAs. In addition, Altera will announce the 40nm HardCopy IV structured ASICs, as well as corresponding software tools for both device types. The families promise to enable a new class of single-chip, multicore and related complex devices.
2006-07-26 Formal verification tool promises finer control
Averant released the next generation of its formal verification tool, offering what the company claims is the industry's first formal tool to give designers fine control over the tool's thoroughness.
2003-06-10 Formal tools won't replace simulation
Formal verification is a valuable adjunct to simulation, but not a replacement for it, according to panelists at the Design Automation Conference.
2004-08-24 FishTail joins 0-In Design check0in partner program
0-In Design Automation Inc. has announced the addition of FishTail Design Automation to the 0-In Check-In Partner Program, which provides EDA partners access to the industry leading Archer Verification system for assertion-based verification (ABV) and formal verification (FV).
2007-09-24 Firms collaborate to address 65nm FPGA design verification
Xilinx Inc. and a group of EDA companies teamed up to define and implement new verification flows to address ultrahigh-density designs of 65nm FPGAs and new emerging FPGA architectures.
2015-09-08 Examining performance in hardware emulators
Emulation performanceor the speed of its executiondepends on the architecture of the emulation system and the type of deployment.
2015-04-24 Examining OS as the hub of hardware emulator
The operating system shields the software from the hardware and assures the compatibility of any new and old software with any new or old hardware platform.
2016-01-04 Examining memory models
Know the qualities you should look for in memory models, and learn about a library touted to deliver the most comprehensive solution of this kind and supports any type of simulation environment.
2005-08-29 ESL tool tames one tough task: On-chip register design
Blueprint, an electronic system level tool from Denali Software, automatically generates and manages the vast number of on-chip control registers that users no doubt find themselves juggling.
2015-05-15 Enhancing analogue design verification using UVM
In this article, we explore an efficient, reusable analogue and mixed-signal verification approach using the Universal Verification Methodology.
2012-07-12 Employ emulation to debug software and hardware at the same time
Here's a guide to using an emulator to ensure the system is truly ready to be committed to silicon.
2005-03-23 Electrical test rolls
EDA startup Knowlent will roll out its first products for the electrical verification of high-speed interfaces.
2006-12-20 eInfochips verification component supports Mentor's Questa
A component that provides building blocks for efficient design-under-test in module and system-level verification for Mentor Graphics' Questa Vanguard program, including assertion testing, is now available from eInfochips Inc.
2008-06-10 eInfochips launches IP tool for improved functionality
EInfochips Ltd launched what it claims as the first SystemVerilog verification IP that will enable designers to better use key SystemVerilog functionality while cutting verification cycle times for designs and serve as blocks needed for DUT for system-level verification.
2003-01-09 EDA's unique opportunity in the silicon value chain
As design sizes shrink toward 90nm, a new set of problems has arisen. Signal integrity, design for test, verification, and design reuse are becoming ever more critical in addressing today's increasing design complexities.
2003-01-03 EDA vendors brace for 90nm challenge in 2003
The ramp-up to 90nm chips will give the electronic design automation industry a strong focus in 2003, according to EDA industry executives and observers.
2004-05-19 EDA vendor, Accellera moves place SystemVerilog at crossroads
Two new developments raise questions about whether the emerging SystemVerilog language is heading for greater harmony or further acrimony.
2003-12-09 EDA startup pioneers assertion-based synthesis
Startup Bluespec Inc. will preview an "assertion-based" synthesis technology next week that it describes as a new approach to chip design.
2011-02-14 DPI processor offers 40Gbit/s wirespeed performance
Cavium Networks' single chip NITROX DPI II processor family works with the company's TurboDPI software to enable inline and coprocessor solutions for enterprise, wired and wireless networks.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top