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2013-01-14 Implementing asynchronous logic in COTS FPGAs
To pave the way for the widespread adoption of asynchronous logic design, Javier D. Garcia-Lasheras has started an open source project.
2006-02-01 Engineer readies tool that generates logic specs
Logic design tool lets users specify transitions for all states and input combinations
2009-06-23 Asynchronous synthesis tool uses standard languages
Tiempo AS will demonstrate what it touts as the first synthesis tool for asynchronous logic that operates from standard design languages at the Design Automation Conference.
2006-01-18 Asynchronous EDA tools coming in Q2, says Silistix
Silistix, a spin-out company from an asynchronous logic research group at the University of Manchester in England, has announced further details of its asynchronous interconnect design tools.
2014-03-07 Silicon Basis lowers SRAM power via standard logic
Silicon Basis built its SRAM on a standard logic process, directing the memory to source power from the logic's voltage source
2010-12-10 Perform asynchronous oversampling in FPGA
Read about the Virtex-6 FPGA SelectIO technology that can perform 4X asynchronous oversampling at 1.25 Gb/s
2001-06-01 LSI Logic's C-Cube bid part of home net push
LSI Logic's move to acquire C-Cube Microsystems is part of a larger strategy to amass key IP components before tackling the market for home-gateway ICs
2002-08-14 LSI Logic offers ADSL modem chipset
LSI Logic Corp. is moving into the standard-chips business for ADSL modems with the introduction of a three-piece chipset
2002-08-21 Fulcrum IC heats asynchronous design debate
A coolly tantalizing alternative to the latest approaches to blazing IC performance is expected to cut this week's sweltering heat at the Hot Chips conference.
2003-04-04 Chip designers debate asynchronous resets
Chip designers are divided when it comes to choosing synchronous or asynchronous resets, according to postings in the latest E-Mail Synopsys Users Group 409 bulletin
2007-03-01 Asynchronous interconnects need innovative tools
Today's EDA tools lack the ability to describe the more complex constraints used by self-timed circuits. Instead, they remain slanted toward the simpler, synchronous circuits commonly used today.
2003-03-10 Asynchronous design demonstrated at 130nm
Fulcrum Microsystems has reported successful characterization of a 130nm test chip carrying its fully asynchronous Nexus crossbar switch block
2004-03-04 Agilent revamps logic analyzer line
Agilent Technologies has elected to shift to a Windows XP environment and to move logic analysis very close to the latest generation of FPGAs
2007-04-02 Efficient 8X oversampling asynchronous serial data recovery using IDELAY
Xilinx Virtex-4 and Virtex-5 devices a have high-precision programmable delay element associated with every input pin. These delay elements, called IDELAY, can be used to implement an oversampler that uses very few FPGA logic resources and, more importantly, just a single DCM and two global clock resources to do 8X oversampling. This solution provides better jitter tolerance than techniques that use multiple DCMs
2004-01-01 Speeding up FPGA clock schemes
One of the most important steps in the design process is to identify how many different clocks to use and how to route them.
2014-05-30 Exploring the micropipeline
The micropipeline is a powerful yet simple design approach enabling the implementation of extremely efficient asynchronous circuits. Here's a review of its underlying concepts
2004-06-01 Synplicity spins Xilinx-specific version of RTL debugger
Synplicity released a version of its Identify RTL debugging software with features targeting users of Xilinx's FPGAs.
2013-10-22 Structural, reset faults in SoC designs (Part 2)
Know some of the basic structural issues in reset architectures used in advanced nanometre scale SoC designs.
2002-10-29 STMicro transceiver offers 3.6V-tolerant I/Os
The company's 74ALVCH16245 16-bit CMOS transceiver features 3.6V-tolerant I/Os and offers a maximum propagation delay of 3ns.
2001-03-28 State machine design considerations and methodologies
This application note describes the various options encountered during the state machine design cycle.
2002-04-19 Philips SiGe process targets optical network chips
Philips Electronics has announced the availability of the QUBiC4G semiconductor process that combines high-speed SiGe technology with the passive component integration, substrate isolation, and dense logic capabilities of their QUBiC4 BICMOS process
2005-03-30 Mixed signal power control is programmable and non volatile
The analog inputs of Lattice's new Power1208P1 device are capable of monitoring power supplies with voltages down to 0.67V.
2004-12-27 How can they learn?
Part Rube Goldberg, part Tinker Toys, Jack's retro toys are taught the basics of digital logic and computer programming in an unusual way
2004-11-03 High-performance DACs support six-, eight-audio channels
Cirrus Logic unveiled two new 24bit, 192kHz, multi-channel digital-to-analog converter ICs, the CS4365 and CS4385
2005-03-28 First PCI 3.0-compliant UART
Exar's XR17V258 UART devices will support 66MHz PCI bus interfacesup to 8 channels with 32bit data.
2006-04-07 Exar announces first integrated 8bit UART, RS-232 transceiver
Exar unveiled what it touts as the industry's first 8bit UART and RS-232 transceiver combination device family.
2006-07-07 Embedded web server rolls for VxWorks real-time OS
Real Time Logic has announced the availability of an embedded web server for the VxWorks real-time OS, which is touted to be the industry's most powerful
2004-05-17 Infineon processor bridges ATM, Ethernet traffic
Infineon has created the specialized processor ConverGate-C, designed to aggregate ATM-based xDSLs and convert the traffic to Internet Protocol on the line card.
2001-03-21 Delta39K and Quantum38K dual-port RAM
This application note provides information and instruction in implementing synchronous/asynchronous dual-port RAM (DPRAM) in Delta39K and Quantum38K CPLDs
2003-01-16 Benefits, risks in 90nm SoC solutions
Depending upon proven capabilities with SoC designs, the cost/benefit of optimization options must be carefully weighed against assumptions on technology maturity.
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