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What does asynchronous mean?
In an asynchronous circuit, parts are largely autonomous. They are not governed by any regular, periodic time-controlling mechanism, such as a clock circuit or signal, but instead need only wait for the signals that indicate completion of instructions and operations. These signals are often specified by simple data transfer protocols.
This digital logic design is contrasted with a synchronous circuit which operates according to clock timing signals.
total search580 articles
2003-07-01 Exar devices suit datacom platforms
Exar Corp. has released what it claims to be the industry's smallest UART package for data communications platforms.
2006-04-07 Exar announces first integrated 8bit UART, RS-232 transceiver
Exar unveiled what it touts as the industry's first 8bit UART and RS-232 transceiver combination device family.
2013-06-13 Example of LPC24XX external memory bus
Here's an example design illustrating how to connect asynchronous and dynamic memory elements to the external memory bus of the LPC24XX.
2000-03-20 Ethernet LAN to ATM WAN
This paper presents a single-chip solution aimed at providing efficient transport between the LAN and WAN networks. The increasing speed and complexity of multiple transport protocols makes the WAN-LAN interface devices critical to the performance and flexibility of communication networks.
2011-07-20 Differences between Maxim's UART devices
Learn how to adapt software and hardware from one UART device to another.
2014-09-24 Designing UART in MyHDL and testing it in FPGA
In this article, we will learn how to capture our very own universal asynchronous receiver/transmitter design using MyHDL, a free, open-source Python library.
2005-02-16 Convergence at last
The latest innovations in SoC, SiP, memory stacks and dense PCBs are enabling the convergence of voice, music, camera and video onto a single platform.
2002-12-02 Comparing priority scheduling with pre-runtime scheduling
In order to provide predictability in a complex hard-real-time system, the major characteristics of priority scheduling approaches must be determined in advance.
2005-04-08 Chipset automates wireless links
TI turned its attention to simplifying applications development for frequency-hopping, spread spectrum 915MHz systems with its Dolphin wireless UART chipset.
2011-05-03 Bsquare rolls next-gen Snapdragon development platform
The MSM8660-based Snapdragon MDP offers new features such as a dual-core CPU that supports asynchronous architecture and console quality and stereoscopic 3D graphics performance.
2003-01-16 Benefits, risks in 90nm SoC solutions
Depending upon proven capabilities with SoC designs, the cost/benefit of optimization options must be carefully weighed against assumptions on technology maturity.
2000-05-03 Architectural considerations for an Internet Protocol (IP) phone processor
This paper begins by discussing the IP-based voice systems technology and the factors which influence the quality of voice IP data transmission. This paper also explains the basic requirements of a VoIP system and the corresponding international standards.
2003-05-07 AKM sample rate converter fits DVDs, DTVs
The AK4121 master-clock-free asynchronous sample rate converter is designed to support the various sampling rates of next-gen DVDs and DTVs.
2002-03-19 ADI ADSL line driver delivers 18V from 12V supply
Designed using Adaptive Linear Power (ALP) architecture, the AD8393 ADSL line driver anticipates signal peaks in the network, and delivers 18V from a single 12V supply when the peak power is needed.
2007-02-28 Using the MAXQ3120 microcontroller's ADC in polled mode
Operating an ADC in polled mode rather than interrupt-driven mode can be preferable in applications where priority or the inherently asynchronous nature of interrupts is a concern. This application note identifies some considerations when using the MAXQ3120 microcontroller's 16-bit sigma-delta ADC in polled mode.
2009-03-04 Using a Micron CellularRAM device with the AMCC PPC405EZ embedded processor
This technical note focuses on the asynchronous/page/burst, 128Mb, CellularRAM 1.5-compliant device, MT45W8MW16B.
2009-11-30 USB audio kit achieves sub-3ms roundtrip latency
XMOS USB audio 2.0 ref design's asynchronous mode is a vital ingredient in the reduction of digital audio jitter which results in superior sound reproduction.
2000-02-23 Understanding the TSB12LV4x Bulky Data Interface
This application note describes the operation and features of the Bulky Data Interface (BDIF) of the TSB12LV4x 1394 link layer controller device family. The BDIF provides a data transfer interface for use with high speed peripherals. The interface can provide sustained data rates up to 160Mbps. In addition, the BDIF has access to an 8KB FIFO which supports isochronous, asynchronous, and MPEG2/DV data transfers.
2006-08-17 Tundra solution targets 32bit PCI bus bridging apps
Tundra said its new Tsi350 is an industry-standard, low-power asynchronous PCI-to-PCI bridge that targets new designs or existing board footprints using standard 32bit 66MHz PCI-to-PCI bridges.
2002-03-01 TTTech, AMS communications processor offers up to 25Mbps data rate
The AS8202 communications processor combines TTTech's Time-Triggered Protocol with support for fault-tolerant bus systems, enabling a data rate of 5Mbps in asynchronous mode and up to 25Mbps in synchronous mode.
2009-05-05 ST10 UART recommendations
This application note gives advice on using the ASC peripherals present in the ST10 and the asynchronous operations will be considered.
2005-06-22 ST unveils new ADSL chipset
STMicroelectronics' CopperWing12e chipset embeds an enhanced Asynchronous Transfer Mode/Internet Protocol cell processor with fast connection speeds and high real-time processing capability.
2007-08-21 SRAMs offer temperature range options
The new 4Mbit asynchronous SRAMs from ISSI are available in commercial, industrial and automotive temperature ranges to support a wide variety of applications.
2006-01-16 SRAM offers upgrade path to 2Mb in same footprint
Mintech introduced a 1M x 32 asynchronous SRAM that is pin-compatible with its 512,000 density SRAMs and can be upgraded to a 2Mb density in the same footprint.
1999-09-09 Self-synchronizing a CDMA cellular network
This paper describes the concept of utilizing the normal messaging of mobile stations operating in an IS-95 CDMA network to transfer time between various BTSs (Base Station Transceivers). IS-95 is a time-synchronous system in that all BTSs operate from a common time reference, which is specified to be the same as the time scale used by the Global Positioning System (GPS). This design choice provides the CDMA network with several advantages over an asynchronous design, but does require some means to distribute time throughout the network.
2008-07-24 Project Galaxy allots $6.4M for GALS research
The EU-funded Project Galaxy has started developing a design process for globally asynchronous, locally synchronous (GALS) architecture chips with novel network-on-chip (NoC) capabilities.
2006-01-18 PMC packs gobs of serial I/O
Concurrent Technologies' 4-channel asynchronous serial communications PMC adaptor is suitable for insertion into CompactPCI or VME bus platforms.
2007-03-08 PCI-to-PCI bridge features low power draw
Tundra's asynchronous PCI-to-PCI bridge offers communications and network equipment customers a competitive, high-quality bridge solution with low power consumption.
2002-06-28 Papers reveal Synopsys, Cadence research projects
Innovation is alive and well as Synopsys Inc. is moving ahead in formal verification, test and synthesis, and Cadence Design Systems Inc. is breaking new ground in timing analysis, asynchronous design and model reduction.
2003-02-21 OSE RTOS suits telecom infrastructure apps
The company's enhanced RTOS and development environment provides fast, asynchronous interprocess communications suited for fault-tolerant operations.
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