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2004-06-10 TSMC selects Atrenta as Reference Flow 5.0 partner
Taiwan Semiconductor Mfg Co. (TSMC) has adopted Atrenta Inc.'s low power and ERC products as key enabling technologies in the company's latest Reference Flow 5.0. Both products from Atrenta include advanced solutions for clock domain analysis, DFT analysis, constraints analysis and automated functional analysis.
2011-05-26 Imec, Atrenta develop exploration flows for 3D ICs
Atrenta and Imec have co-developed a design flow for heterogeneous 3D stacked ICs.
2002-07-12 Atrenta, Xilinx enhance software for Virtex FPGA analysis
Atrenta Inc. and Xilinx Inc. have disclosed the added capabilities and Virtex-specific rules for Atrenta's SpyGlass software.
2012-11-07 Atrenta, TSMC set SpyGlass IP Kit 2.0 release date
The latest software is based on the SpyGlass RTL design platform, the IP Kit 2.0 will by available to all TSMC's soft IP alliance partners on Nov. 20, 2012.
2010-10-27 Atrenta, TSMC cooperate on synthesizable IP
The companies will define a subset of Atrenta's GuideWare methodology for soft IP handoff and IP acceptance that will automatically generate comprehensive reports for each IP block for end customers.
2003-05-21 Atrenta tool scans thousands of flops, targets low-power design
Atrenta Inc. has released a new version of its Spyglass RTL predictive analysis tool targeted at low-power design.
2004-06-08 Atrenta releases RTL checker
Atrenta's assertion-based functional analysis tool checks whether user RTL is functionally correct and fixes problems to minimize iterations between simulation and synthesis.
2005-05-09 Atrenta expands RTL analysis and verification
Claiming new capabilities for IC design, Atrenta rolled out "predictive development" tools for RTL analysis and assertion-based verification last week.
2002-05-23 Atrenta adds logical prototyping to analysis tool
Atrenta Inc. has released a new add-on to its SpyGlass IC prototyping tool that it says will help engineers create a logical prototype of their SoC designs.
2002-11-25 Agere to offer Atrenta predictive analyzer
Agere Systems Inc. has selected Atrenta Inc.'s SpyGlass predictive analyzer as their ASIC handoff tool.
2003-08-07 RTL tool provider snags $5.3M funding
Atrenta Inc., provider of RTL "predictive analysis" solutions, has secured $5.3M in series B venture capital funding.
2007-03-16 New tools solve CDC-analysis troubles
CDCs have become a leading cause of design errors. Errors may even find their way into silicon, necessitating respins.
2013-12-03 RTL signoff: A design imperative
"RTL Signoff" as an established concept has gained significance in the last year. However, writes Atrenta's Piyush Sancheti, does a commonly accepted definition of RTL signoff exist?
2012-06-07 Linting solution speeds design to implementation
Atrenta's Fast Lint methodology for its SpyGlass RTL analysis and optimization platform claims a 4X to 9X speed improvement while still delivering accurate, low noise results.
2004-09-15 From idea to industry inside track
Atrenta's success comes from the idea that 'great riches could be found by scrutinizing RTL code'.
2012-06-21 Acquisition expands Altrenta's RTL platform portfolio
Atrenta says that its acquisition of NextOp Software will accelerate its growth in front end design.
2002-08-28 Xilinx overhauls FPGA software design package
A major upgrade of Xilinx Inc.'s Integrated Software Environment FPGA design tool package features new system-level design capabilities, improved performance, and new utilities to simplify FPGA design.
2014-09-11 When sub-systems are more than just bigger IP
At the end of the day, the reason CPU and GPU sub-systems are not just bigger IP is that they have to be wrapped and optimised to the nth degree to be competitive on Power, Performance, Area/Cost, and Reliability.
2010-02-05 What's in EDA crystal ball?
EE Times presents a discussion with EDA pundits Walden Rhines, Gary Smith, and Joseph Borel on their estimates and predictions for this year's EDA market.
2014-09-17 What does flexoelectricity hold for energy harvesting?
Seen to be rather ambiguous, flexoelectricity enables a dielectric to become electrically polarized when bent and be bent when electrically polarizedmuch like the piezoelectric effect, but different.
2004-10-01 Ventures get capital for a price
There are a lot of startups in EDAprobably too many. If they don't make it, it may sour investors on the sector.
2010-10-07 TSMC expands IP alliance to welcome soft IP
TSMC has now expanded its IP Alliance to incorporate a soft IP program which will improve soft IP readiness for advanced technology nodes and promote earlier time-to-market.
2014-11-20 The ways to verify SoC
In this article, we will start with the discussion on what and why of verification and only then consider the how.
2014-07-10 The semiconductor future according to tech bigwigs, Part 1
The industry is constantly evolving, forging a new path each time, and it is the semiconductor analysts and tech leaders who can indicate the path being taken.
2004-04-06 Synopsys forum updates SystemVerilog support
The message at the Synopsys EDA Interoperability Developer's Forum, convening Thursday (April 1, 2004), is clear; SystemVerilog support is growing.
2002-06-05 RTL-to-GDSII flow shows signs of maturity
The RTL-to-GDSII design flow will take center stage at next week's Design Automation Conference in New Orleans, as several vendors show new technologies intended to solidify an all-in-one flow.
2003-09-01 Predictive analysis for low-power IA designs
Predictive analysis techniques incorporates low-power design techniques and ensures adherence to new design methodologies.
2009-07-28 Power to take center stage at DAC
Power, arguably today's No. 1 headache for designers, will be the theme of workshops, tutorials, meetings, presentations and technical tracks at the 46th Design Automation Conference (DAC).
2004-06-22 Indian software prowess fails to translate to EDA
India's software services firms may be high-profile in the world of IT, but they barely register on the EDA radar.
2007-03-23 Hope fades for IC power standards union
The hoped-for-convergence between two rival IC low-power specifications will not likely take place anytime soon.
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