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2015-07-16 Structural netlist for analogue IP verification
Find out how to achieve more accurate analogue behaviour by using a structural netlist instead of a behavioural model to reduce the number of silicon defects and the verification cycle time.
2013-04-16 MATLAB, Simulink certified for STARCAD-AMS workflow
Japan's Semiconductor Technology Academic Research Centre was able to test the high quality and flexibility of MATLAB and Simulink, allowing them to effectively solve design issues as they arose.
2015-02-12 Verilog-AMS vs SPICE view for power management
Verilog-AMS is a behavioural abstraction of the circuit that sacrifices accuracy for the sake of run time, while SPICE does exactly the opposite. Here's a comparative analysis from a power management perspective
2015-10-12 What you need to know about sensor fusion
Here is a look at the general concept of sensor fusion, the historical perspective, and two detailed casesinertial sensor fusion and image fusion.
2015-04-27 Verilog-AMS vs SPICE view for SoC verification
In this article, we comparatively analyse the usage of Verilog/Verilog-AMS and SPICE views from the perspective of data converters and clocking IPs in an SoC.
2015-03-31 Flying drones, big data fight poaching
SAN Parks (South African National Parks) announced that these unmanned aerial vehicle solutions would now be an integral part of their strategy to combat rhino poaching in the Kruger National Park.
2015-09-08 Examining performance in hardware emulators
Emulation performanceor the speed of its executiondepends on the architecture of the emulation system and the type of deployment.
2013-09-05 Building interrupt responses into embedded SoC
Achieve significant savings in iterative coding, analysis, and debugging time for individual interrupt cases.
2014-10-13 Answering the need for network security through encryption
A new OTN encryption core gives AES-GCM with 96bit IV and a choice of 128bit or 256bit keys, offering privacy as well as confirmation that the decrypted packet has not been altered.
2013-07-22 Virtual design, verification for e-Mobility
Learn how to address many of the emerging engineering challenges that carmakers now face.
2015-05-11 Verilog-AMS vs SPICE view for DDR, LCD verification
In this instalment, we comparatively analyse the usage of both views from the perspective of DDR interfaces, LCD controllers and on-chip memories.
2014-10-27 Smart cities? Singapore plans to become a smart nation
The government introduced a slew of initiatives, including the construction of the enabling infrastructure that will facilitate greater connectivityall to improve the quality of life for individuals and create business opportunities for enterprises.
2015-10-05 MEMS design, manufacturing on the microscale
The microelectromechnical system is a source of wonder in this modern world, so too is its design and manufacturing. Find out why.
2015-02-23 Grasping architectures for ISO 26262 systems
OS architecture is crucial in an ISO 26262 system as it is fundamental to overall system dependability and it determines how easy it is to protect components with different or equivalent ASIL requirements.
2013-12-30 Examining JESD204B converter protocol advances
JESD204 was originally rolled out several years ago, but it has undergone revisions that are making it a much more attractive and efficient converter interface.
2013-07-24 EMC simulation addresses ECU validation issues
A more straightforward validation of electromagnetic compatibility can be achieved by combining tools.
2012-01-04 Boost SDR performance
Here are some examples of how software for system simulation of RF end-to-end architecture design can be used to address the software defined radio design challenges.
2014-11-07 Biology-based approach can protect IoT systems
The size, exponential growth, distributed nature and economics of the Internet of Things present new, arguably paradigm-shifting challenges in security management.
2014-06-05 Accellera updates Verilog-AMS with verification, modelling
The enhanced features of Verilog-AMS 2.4 include supply sensitive connect modules, an analogue event type to enable efficient electrical-to-real conversion and current checker modules.
2013-02-08 Accelerate tester-based silicon debug (Part 1)
Learn about the silicon test and debug phases an SoC must undergo, as well as the techniques and tools available to the test engineer.
2015-12-22 Accelerate compile/verification under Synopsys VCS
Compilation time can be methodically controlled using a tool developed by Synopsys, the Verilog Compiler and Simulator that uses the Pre-Compilation IP technique.
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