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2003-05-27 Bit error ratio BER in DVB as a function of S/N
This application note describes a second, viable approach to generating a defined bit error rate (BER), taking into account signal-to-noise ratio (S/N) deterioration.
2003-12-01 Testing an A/D's power supply rejection ratio
This article describes an easy way to measure the system's AC power supply rejection and quickly determine how badly the power supplies are corrupting the system dynamics.
2004-10-01 Testing W-CDMA user equipment with RMC
Reference measurement channel provides a means to analyze areas of receiver performance in the RF domain.
2011-11-16 Reliability demo of VCSEL devices at 40Gbit/s
The VCSEL devices made from a material at IQE operate at 850nm for short-reach fiber data communication storage area networks.
2006-02-15 PCIe tool delivers in-depth characterization testing
Dishing up parallel BERT software that enables compliance and characterization testing for PCIe, Agilent announces this capability for its existing 81250 series ParBERT.
2005-06-15 Fastest total-jitter measurement?
Offering an measurement technique that promises to reduce test times by a factor of 40, Agilent announced what it claims is the industry's fastest TJ (total jitter) measurement capability for high-performance BERTs.
2009-01-22 BER reference design rolls for 100G Ethernet testing
Inphi Corp. has launched a 28G Bit Error Ratio (BER) Receiver reference design for R&D or production testing of emerging high speed protocols.
2011-12-28 Analyzing jitter, timing in the presence of crosstalk
Here's a new approach to jitter separation in the presence of crosstalk, a growing problem as the number of lanes increases to boost computing system throughput.
2014-01-24 Agilent M8000 allows validation of physical layer designs
The M8000 bit error ratio test solution from Agilent Technologies allows developers and system integrators of multi-gigabit network equipment to characterise and validate physical layer designs and to conduct compliance testing in this area.
2013-01-29 RFP planning wizard integrates VSS design tools
AWR Corporation's latest product is an novative new frequency planning wizard within Visual System Simulator that enables engineers to determine spurious free bandwidths.
2012-01-04 Boost SDR performance
Here are some examples of how software for system simulation of RF end-to-end architecture design can be used to address the software defined radio design challenges.
2010-12-13 Two ways to measure noise figure
Learn about accurate and repeatable methods for measuring noise figure.
2004-01-16 Conexant satellite receiver with FEC decoder
Conexant Systems has introduced an advanced modulation satellite receiver with FEC decoder based on turbo codes.
2015-08-07 Cheaper, denser NAND need better ECC
In this article, we expound why PMC-Sierra switched from Bose-Chaudhuri-Hocquenghem codes to low-density parity check codes for error correction in its solid-state drive controllers
2008-06-13 Analyzing jitter using a spectrum approach
This applications note includes an explanation of jitter and its components; jitter component separation using a spectrum approach; and bit error ratio estimation.
2005-10-18 Agilent's latest serial BERT
Agilent recently announced what it claims as the industry's first high-performance serial bit error ratio tester with advanced jitter generation capabilities for jitter-tolerance testing of serial gigabit devices up to 12.5Gbps.
2014-08-08 Build wireless base station MIMO antennae (Part 1)
Here's a review of the relevant MIMO modes and technology, as well as the advantages of choosing a suboptimal maximum likelihood detector receiver over a minimal mean square error receiver
2004-12-23 Analog decoders outdo digital in wireless test
Advanced digital wireless standards like those overseen by the 3G Partnership Project use iterative communications protocols that provide error correction simultaneously with optimal compression
2013-04-17 20nm planar cell yields 128Gb NAND flash
Know the key improvements and innovations that are needed to produce the smallest 128-Gb, 3 bit-per-cell product
2010-08-02 Low-power, high-speed ADCs comply with JESD204A
Analog Devices Inc. (ADI) has started to sample a pair of low-power, high-speed 14-bit ADCs (analog-to-digital converters) that incorporate the JESD204A data converter serial interface standard
2012-04-03 Developing NAND flash controller with high-level synthesis
Read about the application of a commercial HLS tool to a NAND flash controller with an error correction code block
2012-04-24 TV analyzer aimed at DTV transmitters
The R&S ETC compact TV analyzer supports ISDB-T, DVB-T and DVB-T2, and features spectrum analysis, TV analysis, scalar network analysis and power measurement.
2011-06-08 Test solution validates at 5.8Gb/sec speed
Agilent Technologies announced a comprehensive Mobile Industry Processor Interface (MIPI) M-PHY test solution to help design engineers turn on, debug and validate all layers of mobile devices.
2012-07-09 Tektronix simplifies serial bus debug
Tektronix rolls out upgrades that simplify serial bus debugging.
2006-04-14 Serial IO toolkit simplifies debug of Virtex-4 FX RocketIO transceivers
Xilinx's Serial IO toolkit is designed to reduce the cost and complexity of debugging high-speed serial IO designs.
2007-08-07 PXIT modules enhance optical transceiver testing
Agilent's PXIT modules allow optical transceiver makers to combine key instruments needed to perform required measurements in one mainframe via the same interface to reduce the cost of test and increase production throughput.
2007-08-07 Parade picks Agilent tester for DisplayPort designs
Agilent announced that its Agilent J-BERT N4903A was picked by Parade Technologies for DisplayPort testing.
2015-11-03 Optimising equalisation for FFE, CTLE, DFE
Know the significance of balancing cost and power against CTLE/Tx FFE and the number of DFE taps in a way that reduces ISI without amplifying crosstalk.
2016-05-06 Measuring PAM4 symbol levels
There are different techniques for measuring PAM4 symbol levels such as those offered by IEEE and OIF-CEI. While they are strongly correlated, they're not the same.
2014-11-27 How to achieve 200-400GE network buffer speeds
Know how a serial chip-to-chip protocol, with 200-400 GE data rates and 4.5 B read/write transactions, can be used to eliminate throughput bottlenecks at the processor/external DDR memory interface.
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