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2011-08-26 Test system enables coverage at branch, block level
Wind River has introduced the latest version of Wind River Test Management that identifies high-risk segments in production code and enables optimized testing that focuses on changes between builds.
2012-08-30 Overcoming challenges for SoC verification team
Know the unique problems that SoC verification engineers face and the approach that provides them a level of automation similar to that enjoyed by block-level verification teams.
2004-05-06 Jasper upgrades verification product
Jasper Design Automation will announce the latest release of its JasperGold product enabling what the company calls a provably correct design methodology.
2003-08-06 Startup unwraps power grid planning software
Turning adversity into opportunity, a design engineer laid off last year has developed a block-level power grid noise simulator he had thought about for years.
2010-12-24 Design methods shift to software, part 2
Designing via block level IP integration with virtual platforms shortens the number of steps between design intent and having working hardware and software.
2010-02-19 Dealing with formal verification constraints
Formal model checkers are indispensable, complementing simulation for block-level verification in an ever-challenging design environment. Constraints make a formal tool tick.
2002-02-12 Altera design software reduces compile times by 50 percent
Version 2.0 of the Quartus II SOPC design software is includes the LogiLock design flow that is claimed to improve performance in block-level design by 15 percent, and the fast-fit compile option that reduces compile times by 50 percent.
2008-02-18 Why we need a new analog design flow
Analog-mixed signal designers need a first-time right design methodology now. Why is this familiar cry more urgent and probably truest this time?
2013-05-09 Why stitch and ship is no longer workable
As the systems change, the stitch and ship methodology is leading to increased numbers of costly failures.
2013-04-30 Why flash storage is important to MEMS
Solid state drives operate at higher temperatures, and MEMS devices can withstand that environment because they regulate themselves.
2015-02-25 Violin seeks uptake of all-flash array as primary storage
The company's Flash Fabric Architecture comprises a mesh of thousands of flash dies organised into intelligent flash management units offered at a lower price point.
2007-07-16 Verify designs with assertions
When adopting components of assertion-based verification (ABV) into standard production flows, teams run into several challenges. This article gives tips and tricks when dealing with ABV.
2004-01-01 Verification platform for Jeda language rolls
Jeda Technologies released Jeda-X, a commercial product based on the Jeda hardware verification language.
2007-08-29 Verification kit supports advanced techniques
Cadence Design Systems' new verification kit for SoC designs that aims to enable engineers to adopt advanced verification techniques with reduced risk and deployment effort.
2014-07-17 Utilising ARM Cortex-M based SoCs (Part 1)
Learn how internal SoC peripherals, such as an op-amp, ADC, PWM, and most importantly a processor core, are used to develop a system with the least number of components on the PCB.
2012-11-28 Union Semiconductor turns to West as mobile bogs down
One of the few China fabless chip companies working to develop markets in the U.S. and Europe, Union semiconductor is exploring new customers in security, wireless hotspots and Ethernet.
2011-05-02 Uncovering the mysterious A5
Here's a closer look at Apple's A5, the second-generation processor that powers the iPad 2.
2002-09-16 Toshiba, Neolinear formulate new methodology for Soc design
Toshiba and Neolinear teams up to implement a new AMS design methodology that enables significant analog design reuse.
2007-03-28 Tool taps clock gating for IC power optimization
Claiming breakthrough technology in IC power optimization, Calypto Design Systems is announcing PowerPro CG, a tool that automatically adds clock-gating logic to RTL code.
2005-06-02 Tool brings power analysis to virtual-prototyping phase
Bringing power analysis into the IC virtual-prototyping phase, Silicon Dimensions will announce the latest version of Chip2Nite, a design-planning tool aimed at logic designers
2003-06-02 Tool analyzes power dynamically, at cell level
Apache launched its 2nd product designed for power analysis, the RedHawk-SDL.
2001-04-01 SystemC revision drives toward synchronized system-level design
Synopsys and CoWare launches the SystemC to create a standardized dialect of C/C++ for both hardware and software design. SystemC provides a C/C++ class library that represents hardware concepts such as concurrency for designers to utilize.
2006-01-26 Synthesis tool combines advantages of flat, hierarchical design
It's one thing to design individual blocks for large systems-on-chip and another to tie them together into a working device. Sierra tackles the latter challenge with its Pinnacle Chip Assembly solution.
2005-09-30 Synopsys testbench solution increases verification productivity
Synopsys announced Discovery Pioneer-NTB, a new SystemVerilog testbench automation tool that claims to increase verification productivity and improve the quality of complex SoC and IP designs.
2008-03-07 Synopsys enters embedded memory market
Synopsys Inc. has announced the expansion of its DesignWare IP portfolio with the addition of an SRAM-1T embedded memory IP that is implemented in bulk logic CMOS technology, requiring no additional manufacturing costs.
2002-06-14 Synopsys compiler handles >20 million gate designs
Synopsys Inc. has announced the availability of the Floorplan Compiler, a high-end hierarchical design planner that accommodates >20 million gate designs through smart partitioning.
2003-09-16 SVP is key technology for nanometer IC design
Examine the importance of chip-level architectural issues and the need for physical hierarchy for multi-million gate nanometer SoC design.
2002-11-04 STMicro rolls multiple bank Flash memories
STMicroelectronics has introduced a pair of multiple bank Flash memories targeted at high-performance next-gen mobile phones.
2003-01-15 STMicro Flash memories feature multi-bit cell technology
The company has introduced a family of Flash memories that feature multi-bit cell technology based on its 0.15?m process.
2003-01-23 STMicro bolsters Flash offerings
The company is streamlining its application-specific Flash devices, with one chip line aimed at mobile devices and another at STBs.
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