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2004-04-19 TSMC, Cadence disclose reference flow integration plan
Taiwan Semiconductor Mfg Co. Ltd (TSMC) and Cadence Design Systems Inc. have announced their planned integration of Cadence Encounter RTL Compiler into TSMC's next-generation reference flow
2002-05-30 TSMC adopts Cadence's signal analysis for reference design flow
Taiwan Semiconductor Mfg Co. has adopted Cadence Design System Inc.'s CeltIC signal-integrity analysis solution for its 0.135m reference design flow.
2003-06-23 Synchronicity updates design management suite
The company has announced it has "re-architected" its Developer Suite, which provides engineering project management and design collaboration software
2008-07-02 Mentor seeks advice on Cadence takeover bid
Mentor Graphics Corp. announced that its board has retained Goldman Sachs and Merrill Lynch as financial advisors with respect to Cadence Design System Inc.'s unsolicited bid for the EDA house.
2002-03-20 Cadence upgrades PCB tool flows
Cadence Design Systems has made major upgrades to its Studio and Expert series PCB design flows, adding capabilities to its SpecctraQuest Signal Integrity Expert, Allegro layout tool, and Specctra autorouter
2002-04-24 Cadence unveils latest products for 0.13?m IC design
In a bid to tackle the emerging challenges caused by increasing complexity of IC design and the advance of process technologies, Cadence Design System Inc. has introduced two new products for 0.13?m and beyond IC design. CadenceR SoC Encounter and Cadence First EncounterR Ultra integrate the Cadence SP&R (synthesis/place-and-route) solution with new advanced capabilities and technology from Silicon Perspective Corp. (SPC), which was acquired by Cadence last year.
2002-08-15 Cadence releases revised signal integrity tool
Cadence Design Systems Inc.'s new version of its CeltIC signal integrity solution has greater capacity, performance and accuracy than the previous version of the tool
2005-01-20 Cadence releases design constraint checker
Cadence released a new formal analysis tool that generates, analyzes and validates the quality of design constraints designers use to run synthesis, timing analysis and place-and-route tools
2003-10-22 Cadence launches Chinese IC design institute
Cadence Design Systems has joined with a Chinese consortium to launch the Zhongguancan Cadence Institute of Software Technology (ZCIST
2004-04-12 Cadence comeback strategy tied to platforms
One year after Synopsys Inc. unseated Cadence Design Systems Inc. as the top revenue earner in the design automation industry, Cadence is gearing up for a comeback
2005-10-20 Cadence backs IEEE P1647 e standardization
Responding to user demand for a standard verification language, Cadence Design System, Inc. announced their support for the IEEE P1647 e standardization effort. Cadence also contributed resources for technical editing and program management to ensure the standard is of the highest quality and completed on time.
2003-03-14 Cadence adds wire bonding capability to packaging tool
Cadence Design Systems has added a new wire bonding capability to its Advanced Package Designer for designs using stacked packages
2002-09-23 Cadence adds Plato routing engine to design flow
Cadence Design Systems Inc. is upping the ante in the RTL-to-GDSII IC design tool arena with the latest release of its SoC physical implementation tool
2004-05-21 Aspex uses Cadence encounter platform
Aspex Semiconductor has taped out Linedancer processor from Cadence Design Systems Inc. using 130nm technology at 300MHz, and the Cadence Encounter digital IC design platform
2005-03-21 Wipro, Cadence renew EDA agreement
Tapping into a growing Indian IC design market, Cadence Design Systems Inc. has renewed an agreement giving India-based Wipro Technologies access to its EDA software
2006-12-15 Wipro selects Cadence as primary VLSI vendor
Wipro Technologies, a global independent R&D services provider and the services arm of Wipro Ltd, has chosen Cadence Design Systems as its primary vendor for VLSI and system design solutions.
2007-08-02 Winbond adopts Cadence emulator to ease verification
Cadence Design Systems announced that Winbond Israel has adopted the Cadence Incisive Palladium emulator system for its advanced system-level verification needs.
2005-02-15 Users laud C design in DAC 'trip report
Engineers are warming to C language design tools, according to reviews in the Design Automation Conference (DAC) &quote;trip report&quote; released Friday (Feb. 11) by industry gadfly John Cooley
2006-07-20 TSMC reference flow integrates Cadence platforms
Cadence and TSMC announced the integration of the Cadence's Encounter digital IC design platform and Allegro system interconnect platform into TSMC's Reference Flow 7.0.
2012-05-18 TowerJazz reference design flow tips Cadence tech for power management
TowerJazz's Reference Flow 2.0 power management analog/mixed-signal reference design flow integrates power management devices with control logic
2004-12-21 Toshiba supports Cadence RTL compiler for ASIC design
Cadence Design Systems Inc. announced that Toshiba America Electronic Components Inc. (TAEC) has introduced a design kit to support its custom System-on-Chip (SoC) and ASIC customers using Cadence Encounter RTL compiler synthesis.
2006-02-23 Tool generates verification plans from design specs
Severity One is starting to sell Relay, a tool that produces reusable, coverage-driven verification plans from textual specifications or user input through a graphical user interface.
2006-02-27 TI upgrades Pyramid ASIC design kit
Texas Instruments announced the release of version 5 of the Pyramid ASIC design kit, targeting telecommunications, consumer and wireless infrastructure markets
2002-08-09 TI deploys Cadence verification systems
TI has installed the Palladium design verification systems of Quickturn through the QuickCycles EXtended (EX) Access program
2004-04-02 SystemC tool adds top-down design
CoWare has added graphics-based front-end design software and other features to the System Designer tool of ConvergenSC
2004-05-14 System EDA firm raises $3M for expansion
Beach Solutions Ltd, a developer of system-level EDA tools, has raised $3 million to help expansion in the U.S., the company said Monday, May 10, 2004
2004-02-02 Synopsys, Cadence give nod to SystemVerilog changes
Enhancements based on feedbacks from vendors and users spotlighting some shortcomings in the current ver 3.1, will be implemented in SystemVerilog 3.1a.
2005-01-04 Sun, Cadence partner with Indian firm for VLSI training
Sun Microsytems and Cadence Design have partnered with Veda Institute of Information Technology, based in Hyderabad in southern India, to start the country's first nodal center of competency for research and development in VLSI engineering, design automation and embedded system engineering.
2004-12-30 Sun, Cadence partner with Indian firm for VLSI training
Sun Microsytems and Cadence Design have partnered with Veda Institute of Information Technology, based in Hyderabad in southern India, to start the country's first nodal center of competency for research and development in VLSI engineering, design automation and embedded system engineering.
2003-03-17 STMicro adopts Agilent RF design environment
STMicroelectronics has selected Agilent Technologies' RF design environment (RFDE) for its RF/mixed-signal IC design
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