Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > cadence design systems

cadence design systems Search results

?
?
total search955 articles
2012-07-30 Cadence sees momentum gain for design activity
Cadence reported results that outweighed analysts' expectations urging the company to raise its sales target for the year
2011-04-11 Cadence seeks stronger presence in Asia Pacific
Cadence executive Charlie Huang identifies key EDA growth factors in Asia Pacific, describes the semiconductor landscape in China and reveals Cadence's growth strategies in the region
2014-04-22 Cadence seeks comprehensive verification with Jasper
The combination of Cadence's and Jasper's technologies will result in an inclusive metric-driven verification approach that unites formal and dynamic techniques, accommodating engineers who increasingly adopt formal analysis to complement traditional verification methods
2005-01-28 Cadence RTL compiler supports Sanyo production designs
Cadence Design Systems Inc. revealed that Sanyo Electric Co. Ltd has achieved an important production tapeout with the Cadence Encounter digital IC design platform, including RTL compiler synthesis.
2004-12-23 Cadence RTL Compiler supports Oki Soc design platform
Cadence Design Systems Inc. announced that Oki Electric Ind. Co. Ltd has taped out a chip for Oki's uPLAT SoC design platform with the new low-power capability of Cadence Encounter RTL Compiler synthesis.
2004-02-20 Cadence rolls synthesis tool, new metric
Cadence Design Systems will announce that its Encounter RTL Compiler Ultra synthesis tool supports the VHDL language.
2013-09-10 Cadence rolls out verification IP for HDMI 2.0
The VIP allows designers to quickly and thoroughly verify that their SoCs conform to the HDMI 2.0 specification, accelerating ramp-up to mass production.
2013-10-14 Cadence rolls data converter IP for advanced 28nm node
The data converter family includes the 7bit 3GSPS dual ADC and DAC, 11bit 1.5GSPS dual ADC and 12bit 2GSPS dual DAC aimed at high-speed wired and wireless communications applications.
2003-09-17 Cadence rolls custom-IC tools into one platform
Cadence Design Systems Inc. has linked several acquired technologies with upgraded legacy tools to create an integrated custom IC design platform.
2003-11-14 Cadence reveals plans for SystemVerilog support
Cadence Design Systems has revealed plans to support synthesizable SystemVerilog constructs in the April 2004 release of its products.
2003-03-11 Cadence repurchases SpinCircuit in PLM bid
Cadence Design Systems has quietly repurchased SpinCircuit, an e-commerce company it helped launch in 2000, EE Times has recently learned.
2006-12-01 Cadence releases Virtuoso platform upgrade
Cadence Design Systems recently released an upgraded version of its Virtuoso custom design platformthe Virtuoso V6.1.
2002-08-15 Cadence releases revised signal integrity tool
Cadence Design Systems Inc.'s new version of its CeltIC signal integrity solution has greater capacity, performance and accuracy than the previous version of the tool.
2004-10-25 Cadence releases next-gen HW-based verification system
Cadence Design Systems Inc. released its Palladium II system, an integral part of the company's Incisive functional verification platform.
2011-09-28 Cadence releases expanded verification IP portfolio
The new protocol and memory model verification IP (VIP) will accelerate the adoption of the latest mobile standards, says Cadence
2005-09-02 Cadence reduces design cycles using SensorDynamics
Cadence Design Systems Inc. announced that SensorDynamics, a supplier of integrated microsensors, deployed the Cadence Virtuoso custom design platform for its latest chip designed for intelligent sensor interfaces.
2014-07-16 Cadence RC extraction tool qualified for 16nm FinFET designs
The Quantus QRC Extraction Solution promises to speed design signoff and offers faster runtime for single and multi-corner extraction
2003-08-13 Cadence raising $350M for possible acquisition
Cadence Design Systems Inc. is selling off stock to buy back $100M of its own stock and for &quote;general corporate purposes,&quote; according to a statement released.
2004-11-17 Cadence qualifies extraction tool for process tech
Cadence Design Systems Inc. and Chartered Semiconductor Mfg have jointly qualified the Cadence Fire & Ice QX cell-based extraction tool for Chartered's advanced nanometer processes.
2002-09-25 Cadence qualifies as prime EDA vendor for AMS
austriamicrosystems has qualified Cadence Design Systems Inc.'s analog/mixed-signal solutions as a reference flow.
2004-06-18 Cadence promises full SystemVerilog support
As twenty-six EDA vendors presented their plans for SystemVerilog support at the Design Automation Conference last week, Cadence Design Systems was notably missing.
2014-02-21 Cadence preps Tensilica for "always on" applications
Cadence will run the FreeMotion Library on the Tensilica, offloading the functions from the processor and extending battery life
2003-10-10 Cadence pledges backing for SystemVerilog
Cadence Design Systems Inc. has announced its support for SystemVerilog.
2003-08-15 Cadence platforms adopted by China-based IC design center
Cadence Design Systems Inc. has announced that China Suzhou CAS IC Design Center (SZ-CAS ICDC) has employed Cadence EDA platforms in its IC design platform.
2003-08-04 Cadence platform to be deployed by Global Unichip
Cadence Design Systems has announced that its Encounter Digital IC implementation platform has been selected by SoC design foundry Global Unichip Corp.
2004-02-04 Cadence platform supports 64-bit Linux OS
Cadence Design Systems has released key products of its Encounter digital IC design platform on Intel Itanium 2-based systems running the 64-bit Linux OS.
2007-03-15 Cadence platform enables Taiwan's first 65nm chip design
Cadence Design announced that Global Unichip was the first Taiwan-based design company to complete a successful tapeout of a 65nm device with the use of Cadence Low-Power Solution and SoC Encounter GXL RTL-to-GDSII system
2014-12-15 Cadence platform boasts notable increase in SoC verification
The Perspec System Verifier platform automates system-level coverage-driven test development using constraint-solving technology, increasing productivity in SoC verification.
2004-03-11 Cadence platform accelerates interconnect design
The Allegro system interconnect design platform from Cadence is designed to accelerate high-performance, high-density interconnect design
2005-02-07 Cadence plans restructuring, tips DFM initiative
Buoyed by strong fourth-quarter results, Cadence Design Systems Inc. is going into 2005 with a new organizational structure and a stealth-mode initiative, dubbed Catena, aimed at &quote;manufacturing-aware&quote; design.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top