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2004-04-02 SystemC tool adds top-down design
CoWare has added graphics-based front-end design software and other features to the System Designer tool of ConvergenSC
2004-02-02 Synopsys, Cadence give nod to SystemVerilog changes
Enhancements based on feedbacks from vendors and users spotlighting some shortcomings in the current ver 3.1, will be implemented in SystemVerilog 3.1a.
2007-03-16 Stir manufacturing into design effectively
Semiconductor companies looking to maximize yield will need to deploy more effective methods to account for manufacturing effects early in IC development.
2003-08-19 Startup turns to China for analog design suite
Paragon IC Solutions is a two-year-old EDA startup that's selling an analog IC design suite with a 13-year heritage
2004-05-03 Startup looks to fill Cadence CCT vacuum
ConnectEDA aims to fill a gap left when Cadence stopped making its CCT autorouter available for sale by competing EDA vendors in the late 1990s
2004-03-01 Starc to release Starcad-21 design methodology
Semiconductor Technology Academic Research Center will release v1 of a chip design methodology that covers silicon implementation from RTL to GDSII
2013-07-31 ST, ARM and Cadence team up for tool, model interoperability
The collaboration of ST, ARM and Cadence aims to increase model and tool interoperability for electronic system-level (ESL) design at the transaction-level
2013-07-31 SpeedBridge adapter enables PCIe 3.0 design verification
The SpeedBridge Adapter for PCIe 3.0 provides easy bring-up and fast debug of PCIe-based designs when used with a Cadence Palladium Verification Computing Platform
2011-02-07 Solution speeds billion-plus gate design at 28nm
Cadence Design Systems Inc. has announced that it is advancing the design of giga-gate/gigahertz SoCs with digital end-to-end flow at 28nm.
2009-05-25 Software tools speed up design process
EDA software vendor Cadence Design Systems has introduced two tools aiming at speeding up the design process.
2010-12-06 SMIC chooses Cadence for 65-nm reference flow
Cadence Design Systems, Inc., has just announced that SMIC has adopted Cadence Silicon Realization products for the DFM and low-power technology at the center of SMIC's 65-nanometer Reference Flow 4.1.
2002-08-29 SiS adopts Cadence technology for graphics IC design
Silicon Integrated Systems Corp. has standardized on Cadence Design Systems Inc.'s First Encounter, for the design of complex graphics ICs.
2006-02-08 Sirific used Cadence's simulator in designing its RF transceiver
Cadence announced that Sirific has designed its single-chip CMOS RF transceiver for HSDPA/WEDGE using Cadence's Virtuoso UltraSim Full-chip Simulator for FastSPICE simulation
2002-04-29 Simplex purchase expands Cadence's technology trove
In announcing its intention to purchase Simplex Solutions, Cadence Design Systems has set its sights on some key EDA and silicon architecture technology.
2001-05-16 Sequence Design offers tool for timing closure
Sequence Design has combined different technologies in a "design closure" product that can optimize timing and signal integrity concurrently before and after routing
2015-10-20 Sensory brings face authentication software to Cadence DSPs
Cadence and Sensory said the technology makes it easier for mobile designers to cut the power needed for face authentication to unlock a mobile phone, tablet, or any IoT device using a standard camera
2012-02-10 Samsung, Cadence partner in nanometer SoC design
The companies will collaborate on a design-for-manufacturing (DFM) infrastructure to tackle physical signoff and electrical variability optimization for 32, 28 and 20nm ICs
2007-07-11 RTL synthesis tool eases chip-level interconnect design
Claiming a new approach that helps solve problems with chip-level interconnect, Cadence Design Systems is announcing a new component of its RTL synthesis tool, the Cadence Logic Design Team Solution.
2006-06-28 Routing solution speeds design to manufacturing
The Cadence Precision Router speeds design and manufacturing convergence for advanced mixed-signal, analog and custom digital designs
2003-01-31 RLC extraction tool supports Cadence, Mentor flows
Sequence Design has announced an RLC extraction tool that supports large mixed-signal designs in both Cadence and Mentor flows
2002-05-23 Rival RF design flows get a boost
Two former software partners will square off at the Design Automation Conference next month with their respective RF IC design and simulation tools
2008-11-07 Restructuring befalls Cadence
Cadence will undergo restructuring, which is designed to refine the company's strategy, streamline the business and improve operational execution and financial performance
2006-09-01 Restricted design rules challenge DFM
The recent Design Automation Conference made it clear that the EDA industry is counting on DFM for a much-needed boost. But the RDRs that are quietly emerging for 45nm and smaller geometries may reduce the need for some DFM tools and techniques, some observers say
2015-09-16 Resolving giga-scale challenges in memory design
Advanced designs are more complex and larger than ever before, and designers are balancing between accuracy and performance for large scale memory simulation and verification.
2007-06-21 Reported Cadence private-equity buyout hangs
Price wrangling between two private equity firms has suspended talks of a possible buyout of Cadence Design Corp., Reuters reported
2004-10-07 Renesas standardizes on Cadence MaskCompose
Renesas Technology Corp. has standardized Cadence Design Systems Inc.'s MaskCompose for automated reticle design synthesis in its 90nm design flow.
2006-08-18 Realtek, Cadence collaborate on formal verification design
Cadence Design and Realtek Semiconductor announced that they have collaborated to successfully reduce the risk of functional errors on its pilot multi-supply voltage design
2007-09-06 Rambus, Cadence partner on verified PCIe solutions
Rambus and Cadence Design Systems have collaborated to develop fully integrated and independently verified PCIe solutions.
2015-01-14 Processors from Cadence offer local memory power efficiency
The Tensilica Xtensa processors enable users to create innovative custom processor instruction sets with up to 25 per cent less processor logic power consumption.
2001-04-15 Process design kits take aim at custom ICs
This technical article describes Cadence Design Systems' process design kits for 0.25?m and 0.18?m process simulations.
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