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2010-08-27 Magma Design Automation joins Si2's DFMC
The coalition also announces a 60-day review period for the first release of OpenDFM, a high-level DRC language that can be translated into a variety of proprietary verification languages.
2007-05-16 Low-power IC design kit enables representative design
The Low-Power Methodology Kit from Cadence Design Systems includes a wireless "representative design" implemented using multiple supply voltage and power shutoff methods.
2008-12-31 Low-power design binds chips, software
There's a nagging awareness that every new gadget consumes more energy, adding to the carbon footprintand these footprints seem to be getting larger. It's high time we made system design more power efficient
2006-05-11 KPIT Cummins adopts Cadence AMS kit
The Indian arm of Cadence announced that KPIT Cummins has adopted its AMS Methodology Kit to help its analog mixed-signal designers simplify the application of Cadence technology
2006-08-11 Korean foundry teams up with Cadence on process design kit
Dongbu Electronics said it has developed process design kits (PDKs) for high-voltage semiconductor devices
2007-07-25 Jazz adopts Cadence RF, AMS design kits
Jazz has put its faith behind Cadence's RF and AMS design kits, offering its customers a more streamlined design cycle and faster time-to-market
2008-07-14 Japanese design services firms sign up for PFI
Three Japanese design services company have recently joined the Power Forward Initiative (PFI), and they will be offering Common Power Format (CPF)-enabled low-power design capabilities to their customers
2008-01-24 Japan's Starc uses Cadence's CPF tech in ref flow
Cadence Design Systems announced that Japan's Starc has released its next-generation ultralow-power Pride reference flow V1.5, incorporating the CPF-based Cadence Low-Power Solution.
2007-06-06 Is Cadence thinking of traversing the private route
Cadence Design Systems Inc. is reportedly in talks with equity firms Kohlberg Kravis Roberts and The Blackstone Group to go private.
2008-06-18 IPL Alliance's 'interoperable' ref flow puts pressure on Cadence
The analog EDA market is suddenly generating a buzz, as a number of forces unite to advance the technology and threaten Cadence's stranglehold. Ciranova, Magma, Synopsys and TSMC are among the members of the IPL alliance with tools to compete with Cadence
2005-12-20 Inphi tapes out high-speed chip with Cadence platform
Cadence announced that Inphi has successfully taped out a complex high-speed chip using the Cadence Encounter digital IC design platform
2005-05-02 Initiative brings low power to mainstream design
Suppliers say collaboration is the best way to make low-power design accessible to mainstream IC designers
2004-04-26 Improved Cadence results suggest EDA rebound
Cadence Design Systems posted nearly flat year-to-year revenues and a $9 million loss in the first quarter of 2004, but it's a significant upward trend following a period of declining revenues.
2015-03-12 Implementation system from Cadence boosts turnaround time
The Innovus Implementation System offers typically 10 to 20 per cent better PPA and up to 10X full-flow speedup and capacity gain at advanced 16/14/10nm FinFET processes and established process nodes.
2013-01-24 Imec, Cadence team up for DFT solution for 3D memory
Cadence's and imec's solution includes generation of DRAM test control signals in the logic die and inclusion of the DRAM boundary scan registers test access mechanisms of the 3D test architecture
2003-03-28 IC, package co-design proving elusive, techies say
IC package design has become a huge bottleneck for getting chips out the door, but there are few automated tools that can help, according to panelists at the International Symposium on the Quality of Electronic Design
2006-10-18 IC design tool touts process-aware DFM
Synopsys two "process-aware" tools that help custom- and analog-IC designers analyze the impact of transistor variability on circuit layouts.
2004-06-10 IBM, Intel bare mobile workstation for design engineers
IBM and Intel Corp. have collaborated on a new Linux-based mobile workstation pilot designed to increase the productivity of engineers working on EDA.
2009-01-13 How will Tan lead Cadence's resurgence
Cadence's board appointed one of its own to the top job, saddling him with the daunting task of leading Cadence's resurrection
2010-07-21 Hitachi implements Cadence verification system
Transaction-based acceleration technology is being used to implement the system-level verification environment for Ethernet routing/switching products.
2005-08-26 HiSilicon partners with Cadence, SMIC
HiSilicon Technologies Co. Ltd has produced a high-performance communications device, using the Cadence Design Systems Inc.
2005-02-16 Harvard Thermal tool integrates with Cadence package designer
Harvard Thermal announced the direct integration of Package Thermal Designer V2.0 with Allegro Package Designer from Cadence
2008-09-19 Group readies guide kit for SOI circuit design
The SOI Consortium, an industry group set up to promote the use of designs on silicon-on-insulator wafers, has announced the availability of the first chapters of its SOI Implementation Guide.
2003-12-26 Greek EDA startup offers RF design tool
Helic SA has launched an inductance-modeling tool that the company says will slash development costs for wireless transceiver designs.
2012-06-04 Globalfoundries to demo enhanced silicon-validated design flow
According to the company, the flow provides proven and complete front-to-back support for advanced analog/mixed-signal (AMS) design using the industry's latest design automation technology
2005-08-02 Global UniChip improves silicon quality with Cadence tech
Cadence Design Systems Inc. disclosed that Taiwan-based Global UniChip Corp. has adopted Cadence Encounter RTL compiler global synthesis, part of the Encounter digital IC design platform, to improve the quality of silicon (QoS) of its hardened IP.
2006-06-01 Give PCB computer-aided design its due
PCB CAD gets no respect. With about 12 percent of overall EDA industry revenue, it is marked by sluggish growth, little or no startup activity and few announcements of new technology.
2005-08-03 Fujitsu to ship structured ASIC built using Cadence
Cadence Design Systems Inc. and Fujitsu Microelectronics America Inc. (FMA) will ship initial production volumes of structured ASIC using Cadence Encounter digital IC implementation this month.
2002-11-20 Fujitsu deploys Cadence analysis tools on ASICs
Fujitsu Ltd has deployed Cadence Design Systems Inc.'s VoltageStorm and SignalStorm as the standard power verification and nanometer delay calculation solutions for its high-end ASICs.
2006-01-26 Fujitsu adopts Cadence Encounter GXL
Cadence announced that Fujitsu has adopted its Encounter digital IC design platform in its new internal reference design flow targeted at 65-nanometer chips
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