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2002-10-02 FTD adopts Cadence design flow
FTD Technology Pte Ltd has selected Cadence Design Systems Pte Ltd's front-to-back design and verification flow as its primary platform for digital, analog, mixed-signal, and RF IC design.
2005-11-15 Freescale, Cadence make 'single vendor flow' tool deal
Freescale Semiconductor Inc. has closed a multi-year deal with Cadence Design Systems Inc. that is reportedly worth as much as $120 million but could sharply cut EDA costs for Freescale.
2004-10-08 Focus partners with Cadence on enhanced UWB for video
Focus Enhancements announced plans on Monday (Oct. 4) to partner with Cadence Design Systems to provide design services for Focus's proprietary ultrawideband chips.
2007-09-24 Firms collaborate to address 65nm FPGA design verification
Xilinx Inc. and a group of EDA companies teamed up to define and implement new verification flows to address ultrahigh-density designs of 65nm FPGAs and new emerging FPGA architectures.
2006-05-03 Fastrack Design standardizes on Cadence Fire & Ice QX Extraction
Cadence Design Systems Inc. announced that Fastrack Design Inc. is using Cadence Fire & Ice QX cell-based extraction technology to tape out a 65nm design for a consumer product.
2005-12-22 Faraday tapes out ASIC production chips with Cadence platform
Cadence announced that Faraday has taped out ten 130nm ASIC production chips with the Cadence Encounter digital IC design platform
2005-07-15 Epson doubles productivity using Cadence RTL compiler
Japan-based electronics device provider Seiko Epson Corp. (Epson) disclosed that it has doubled in the production tapeout of high-volume LCD controller chip using Cadence Design Systems Inc.
2012-11-27 Electrically-aware design enhances AMS ICs
Implementing electrically-aware design means every physical design decision regarding placement and routing is analysed in terms of its impact on electrical performance and reliability
2005-09-09 Elan verifies embedded memories using Cadence's tools
Elan Microelectronics Corp. has validated its standard cell libraries and embedded memories using the Cadence Design Systems Inc.'s Encounter Conformal custom equivalence checking solution.
2006-11-14 EDA panelists call for standardized process design kits
Standardization of foundry process design kits will provide major benefits for analog and custom IC designers, according to panelists at the Synopsys EDA Interoperability Developer's Forum
2013-03-21 EDA industry needs a makeover, says Cadence CEO
Cadence CEO Lip-Bu Tan talks about the lack of start-ups, the rising cost of chip design and the need to reposition the EDA industry for growth at the annual CDN Live event
2002-04-26 EDA consolidation continues as Cadence buys Simplex
The consolidation of the electronic design automation industry advanced on two front Wednesday (April 24), when Cadence Design Systems Inc. said it will acquire verification specialist Simplex Solutions Inc. for $300 million, or $18 per share of Simplex stock. Earlier, Mentor Graphics Corp. announced plans to purchase Innoveda Inc.
2006-05-26 Dongbu, Cadence offer RTL-to-GDSII reference flow
South Korean foundry Dongbu Electronics said that it has collaborated with Cadence Design Systems Inc. to jointly develop the DBE 130.2 reference flow.
2013-03-11 Design, verification IP aimed at Mobile PCIe
The Cadence M-PCIe IP and VIP solution enables the PCI Express architecture to operate over MIPI M-PHY, extending battery life of mobile devices such as thin laptops, tablets and smartphones
2005-10-11 Design, manufacturing worlds collide at Bacus
If there was a shred of doubt remaining about the magnitude at which IC design and manufacturing convergence is taking place, it was laid to rest last week (Oct. 3-7) at the 25th annual Bacus Photomask Technology symposium in Monterey, Calif
2008-06-12 Design tools eye ARM core for various apps
Cyclos announced a proof-of-concept processor implementation using its platform and design flow. This can be used to achieve low-power, resonant-clock implementations of synchronous ASICs and SoCs without changes to their development and verification environments
2012-05-17 Design suites hasten system integration
Cadence's SDS and Verification IP Catalog have been expanded to give engineers the ability to go beyond simulation to speed verification of large-scale SoCs, subsystems and systems
2015-01-29 Design solutions accelerate design signoff, analysis
The Sigrity Parallel Computing 4-pack and the Sigrity System Explorer from Cadence claim to speed up product creation efficiency by improving signoff-level PCB extraction accuracy
2006-06-16 Design role drives 'new Europe
Danube is riding a wave of economic expansion, fueled largely by the emergence of Hungary and neighboring countries as a hub for electronics design and development
2006-11-16 Design RFICs with greater speed, accuracy
In RFIC design, a "meet-in-the-middle" approach balances top-down fast design processes with bottom-up silicon accuracy to produce a predictable schedule, leading to first-pass silicon success
2012-04-09 Design IP supports LPDDR3 memory standard
The controller and PHY IP solution from Cadence claim to offer high bandwidth and low power consumption required by smartphones and tablets
2006-07-20 Design forum is heavy on ESL this year
The Design Automation Conference next week in San Francisco, California comes with a program heavy on ESL and embedded systems design, design-for-manufacturability, power-aware design and verification. See the details inside
2010-07-29 Design flow optimizes partial reconfiguration FPGAs
Xilinx releases a streamlined design flow for its FPGAs that support partial reconfiguration and offer on-site programming and re-programming
2003-09-16 Design challenges and sign-off criteria in nanometer era
In nanometer era, traditional STA and physical verifications are no longer sufficient. The nanometer sign-off flow must comprise SI-validated analysis engines that account for the interactions of multiple-noise sources.
2005-06-01 Design and verification with Cadence's Virtuoso AMS Designer
This article explains the different 'use model' requirements for the simulator to accommodate its users, the mixed-signal system architect, the model developer, the analog and digital design engineers and the verification engineer
2000-12-01 Deep signal and design integrity assured in SoCs
This technology news article describes the issues related to SoC designs and the corresponding solution to each.
2006-09-20 DDR2 IP from Cadence speeds design process
Cadence Design Systems has announced the availability of an IP portfolio intended to enable engineers to optimize DDR2 interfaces on PCBs and expedite the design process.
2004-01-09 Cypress adopts Cadence extractor for 130nm, 90nm flows
Cypress Semiconductor Corp. has adopted the latest version of Cadence Design Systems' Fire & Ice QXC as the sign off cell-based extractor in its 130nm and 90nm flows.
2008-10-21 CTO junks calls to spin off Cadence
Responding to harsh criticism touched off by the departure of senior executives, the chief technology officer of Cadence Design Systems Inc. dismissed calls to spin off parts of the EDA company.
2005-07-20 Credence, Cadence validate flow for faster yield diagnostics
Credence Systems Corp. has validated a yield improvement flow between their Sapphire test platform and Cadence Design Systems Inc.'s Encounter test.
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