Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > cadence design systems

cadence design systems Search results

?
?
total search955 articles
2007-12-12 Cadence, ARM co-develop multicore ref design kits
Cadence Design Systems Inc. and ARM have jointly developed reference methodologies, one for the ARM11 MPCore multicore processor and the other for low-power implementation of the ARM1176JZF-S processor.
2002-02-19 Cadence, Agilent to speed electronic design in wireless, wireline industries
Cadence Design Systems Inc. and Agilent Technologies Inc. have signed a multi-year technology alliance aimed to accelerate electronic product development in the communications industry.
2001-05-01 Cadence, Agere tool would foster IC co-design
This article describes the Cadence and Agere team-up to develop a tool with chip I/O planning capabilities
2006-12-12 Cadence, Advantest ink car electronics testing partnership
Cadence Design Systems and Advantest Corp. announced a collaborative partnership to deliver a methodology for zero-defect testing of digital automotive electronics.
2005-07-27 Cadence, Accent, ARM improve low-power design
Cadence Design Systems Inc. disclosed that Accent has validated a low-power design flow using its Encounter digital IC design platform and ARM Artisan physical IP.
2006-02-17 Cadence's Virtuoso RET Suite puts 'design back into DFM
Cadence introduced its Virtuoso Resolution Enhancement Technology Suite, which integrates lithography awareness directly into the Cadence Virtuoso custom design platform
2003-08-14 Cadence's extractor fit for copper
Cadence Design Systems' latest Fire & Ice QXC cell-based extractor release includes enhancements and improvements in accuracy.
2005-06-10 Cadence's Encounter supporting Virage Logic's IPrima cell library
Cadence Design Systems Inc. and Virage Logic Corp. announced that Cadence's Encounter low-power digital IC design flow now supports power saving features of Virage's IPrima mobile semiconductor intellectual property (IP) platform's low-power standard cell library
2013-12-16 Cadence's embedded processors go mano-a-mano
The Tensilica and Synopsys ARC can have as many as 30 controller cores outside the main CPU, handling data movement and signal processing with higher clock rates and higher memory bandwidth.
2013-05-22 Cadence's closure tool speeds chip designs to fabrication
The Tempus Timing Signoff Solution is a new approach to timing signoff tools that enables customers to shrink timing signoff closure and analysis for faster tape-out.
2001-05-01 Cadence's 'all-in-one' tool gets skeptic reviews
Cadence's Integration Ensemble (IE) is the first single tool that can take a hierarchical chip design all the way from synthesizable RTL code through a GDSII layout file and designers are raising an eyebrow if it will perform as well as it promises
2005-08-18 Cadence Virtuoso speeds up Cray's supercomputer development
Cadence Design Systems Inc. and supercomputer provider Cray Inc. have completed a project that migrate the full-custom layouts of the memory arrays and cell libraries.
2005-06-13 Cadence Virtuoso NeoCircuit completes Oki IP analog designs
Cadence Design Systems Inc. and Oki Electric Co. Ltd have disclosed that Oki achieved five times faster design turn-around-time for its analog blocks than with its previous design methodology and has completed 30 reusable analog IP designs using Cadence Virtuoso NeoCircuit technology.
2008-07-16 Cadence Virtuoso aids analog, mixed-signal SoC designs
The latest version of Cadence Design Systems Inc.'s Virtuoso custom design platform has been deployed by Matsushita Electric Industrial Co. Ltd for analog and mixed-signal advanced node designs.
2003-03-05 Cadence verification platform has unified methodology
Cadence Design Systems Inc. has launched its Incisive verification platform that supports a unified verification methodology for the embedded software, control, data path, and analog/mixed-signal/RF design domains.
2004-11-04 Cadence uses Sandwork analysis tool for Virtuoso platform
Cadence Design Systems Inc. has integrated Sandwork Design Inc.'s WaveView analyzer into its Virtuoso Aptivia specification-driven environment and Virtuoso UltraSim for FastSPICE simulation.
2002-03-20 Cadence upgrades PCB tool flows
Cadence Design Systems has made major upgrades to its Studio and Expert series PCB design flows, adding capabilities to its SpecctraQuest Signal Integrity Expert, Allegro layout tool, and Specctra autorouter.
2003-09-12 Cadence upgrades OrCAD PCB products
Claiming new features and improved tool integration, Cadence Design Systems announced the 10.0 release of its Windows-based OrCAD tool suite.
2014-05-21 Cadence upgrades FastSPICE with mixed-signal design support
The upgrade enables multi-core simulation to provide the additional performance scalability required in mixed-signal circuits.
2005-12-08 Cadence upgrades Encounter RTL compiler
Cadence announced an upgraded version of its Cadence Encounter RTL Compiler global synthesis technology that helps designers deliver smaller, faster and cooler chips in less time
2013-01-30 Cadence unveils Virtuoso Advanced Node for 20nm
Cadence Design Systems has taken the wraps off Virtuoso Advanced Node, which enables the development of complex mixed-signal chips.
2013-08-08 Cadence unveils VIP Models for latest memory standards
Cadence Design Systems latest verification IP (VIP) models support the LPDDR4, Wide I/O 2, eMMC 5.0, HMC and DDR4 LRDIMM standards.
2006-02-03 Cadence unveils new silicon-proven full-chip optimization system
Cadence Design Systems announced its new manufacturing-aware chip optimization product Cadence Chip Optimizer, which is a silicon-proven full-chip optimization system.
2014-01-15 Cadence unveils Incisive 13.2 for SoC verification
The Incisive 13.2 platform from Cadence Design Systems offers features two new engines and additional automation features to speed SoC verification closure.
2004-12-28 Cadence unveils 'first yield diagnostics tool
Cadence Design Systems' Encounter Diagnostics is touted by the company to be the industry's first yield diagnostics tool.
2004-03-12 Cadence unveils "on-target" system interconnect
There is a major bottleneck between system interconnect design and today's complex ICs which delays time-to-market for electronics companies
2003-11-14 Cadence tool tackles signal integrity issues
Cadence Design Systems has released a new version of its SpecctraQuest toolset to allow EEs designing PCBs to deal more proactively with the signal integrity issues that pop up with high-speed designs.
2008-08-27 Cadence tool steps up IC package, SiP designs
The release of SPB 16.2, due in November of this year, from Cadence Design Systems, delivers advanced IC package/system-in-package miniaturization, design cycle reduction and DFM-driven design, along with a new power integrity modeling solution.
2006-09-14 Cadence tool seen to hasten hardware assistance adoption
Cadence Design Systems believes its next-generation series of Incisive Xtreme accelerators/emulators can remove the traditional barriers to mass adoption of hardware assistance by design teams.
2005-02-01 Cadence tool aims to tackle parasitics in RF design flow
The new release from Cadence Design Systems Inc. addresses the leading cause of wireless design failures.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top