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2003-09-10 Xilinx upgrades ISE FPGA design suite
Xilinx Inc. has improved clock performance, software run-time and area utilization in its Integrated Software Environment FPGA design suite
2005-03-21 Wipro, Cadence renew EDA agreement
Tapping into a growing Indian IC design market, Cadence Design Systems Inc. has renewed an agreement giving India-based Wipro Technologies access to its EDA software.
2006-12-15 Wipro selects Cadence as primary VLSI vendor
Wipro Technologies, a global independent R&D services provider and the services arm of Wipro Ltd, has chosen Cadence Design Systems as its primary vendor for VLSI and system design solutions.
2007-08-02 Winbond adopts Cadence emulator to ease verification
Cadence Design Systems announced that Winbond Israel has adopted the Cadence Incisive Palladium emulator system for its advanced system-level verification needs.
2008-07-25 What has driven Cadence to buyout Mentor
Although I have heard from a few financial analysts who think the acquisition is good for Cadence and for the industry, I continue to believe it will not work even if classical investment theory says it should
2003-07-29 Visualization tool adds PCB design support
AutoVue, a widely-used visualization and collaboration tool, is targeting EDA in its latest release.
2005-02-15 Users laud C design in DAC 'trip report
Engineers are warming to C language design tools, according to reviews in the Design Automation Conference (DAC) &quote;trip report&quote; released Friday (Feb. 11) by industry gadfly John Cooley
2013-07-18 UMC adopts Cadence's DFM flows for 28nm node
The flows address both random and systematic yield issues and incorporate DFM prevention, analysis, and signoff capabilities.
2003-03-13 TTPCom acquires Cadence 802.11 WLAN IP
TTP Communications plc has acquired full ownership of the 802.11 WLAN intellectual property developed by Cadence Design Systems Inc.
2007-06-28 TSMC, Cadence team on 65nm wireless design flow
Cadence and TSMC have teamed on nanometer wireless design and produced a new TSMC 65nm RF PDK compatible with the new Cadence Virtuoso custom design platform.
2004-04-19 TSMC, Cadence disclose reference flow integration plan
Taiwan Semiconductor Mfg Co. Ltd (TSMC) and Cadence Design Systems Inc. have announced their planned integration of Cadence Encounter RTL Compiler into TSMC's next-generation reference flow.
2005-06-13 TSMC releases reference design flow for 65nm processes
Taiwan Semiconductor Mfg Co. Ltd has released version 6.0 of its reference flow, the sequence of EDA tools that the world's largest foundry recommends for its 65nm manufacturing processes.
2006-07-20 TSMC reference flow integrates Cadence platforms
Cadence and TSMC announced the integration of the Cadence's Encounter digital IC design platform and Allegro system interconnect platform into TSMC's Reference Flow 7.0.
2007-07-16 TSMC pulls curtains off 45nm design process
Taiwan Semiconductor Manufacturing Co. Ltd unveiled its latest and most ambitious design methodology for IC production at the challenging 45nm node
2003-06-04 TSMC latest reference flow adopts Cadence platform
TSMC has selected Cadence Design Systems Inc.'s Encounter digital IC design platform as an integral part of TSMC's latest Reference Flow 4.0.
2005-10-06 TSMC approves X Architecture design
Taiwan Semiconductor Manufacturing Company (TSMC) disclosed on Oct. 4 that they are ready to accept 90nm X Architecture designs.
2002-05-30 TSMC adopts Cadence's signal analysis for reference design flow
Taiwan Semiconductor Mfg Co. has adopted Cadence Design System Inc.'s CeltIC signal-integrity analysis solution for its 0.135m reference design flow.
2012-05-18 TowerJazz reference design flow tips Cadence tech for power management
TowerJazz's Reference Flow 2.0 power management analog/mixed-signal reference design flow integrates power management devices with control logic
2005-01-27 Tower Semiconductor strengthens design center program
Tower Semiconductor Ltd announced a major expansion of the Tower Authorized Design Center (TADC) program, naming Cadence Design Systems Inc., QThink, QualCore Logic and SliceX as design center partners.
2003-06-27 Tower PDKs simplify design environments
Tower Semiconductor Ltd. and Cadence Design Systems have announced the availability of the TSL018 and TSL035 foundry-level Process Design Kits that eliminate the need for users to create their own "views" of the Tower technologies in their design environments.
2002-08-01 Toumaz design flows based on Cadence tools
Toumaz Technology Ltd is developing AMx systems with front-to-back analog design flows based on the tools and methodology services by Cadence Design Systems Inc.
2008-01-31 Toshiba, Cadence collaborate on 65nm design
Cadence Design announced that Toshiba has deployed Cadence Virtuoso simulation technology to provide its analog and mixed-signal chip designers an easy-to-use and accurate reliability analysis flow.
2004-12-21 Toshiba supports Cadence RTL compiler for ASIC design
Cadence Design Systems Inc. announced that Toshiba America Electronic Components Inc. (TAEC) has introduced a design kit to support its custom System-on-Chip (SoC) and ASIC customers using Cadence Encounter RTL compiler synthesis.
2006-08-30 Toshiba adopts Cadence solution for 65nm design
Cadence Design Systems announced that Toshiba has adopted Cadence QRC Extraction for its most advanced 65nm design flows.
2006-02-23 Tool generates verification plans from design specs
Severity One is starting to sell Relay, a tool that produces reusable, coverage-driven verification plans from textual specifications or user input through a graphical user interface.
2002-08-09 TI deploys Cadence verification systems
TI has installed the Palladium design verification systems of Quickturn through the QuickCycles EXtended (EX) Access program
2007-03-27 The dilemma of two languages in low-power design
EDA users may not like it, but when it comes to low-power design they will probably have to speak two languages: CPF and UPF
2003-01-08 Tharas signs ICON Design as distributor in India
Tharas Systems Inc. has named ICON Design Automation Pvt. Ltd as its distributor in India
2005-08-31 Tensilica enhances methodology for 90nm design flow
Tensilica has enhanced its automated configurable processor design methodology to account for common IC design challenges with 90nm process technology
2004-01-14 Tanner adds design tool
Providing a low-cost alternative for IC DRC, Tanner EDA has introduced HiPer Verify, the first product in the company's new HiPer line of layout and verification products.
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