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2005-10-11 HDL tool suite cuts cycle times, respins
Mentor Graphics announced the release of a new concurrent design checking and creation environment, available in the latest version of the HDL Designer Series tool suite.
2006-07-18 DRC tool meets yield challenges of nanometer era
Mentor Graphics said its Calibre nmDRC tool redefines the traditional design rule checking (DRC) step to solve the yield challenges of the nanometer era
2004-09-29 Xilinx tool suite targets system-level design
Xilinx introduced v6.3i of the Platform Studio for system-level embedded processing design on Xilinx Platform FPGAs.
2015-08-20 Using DRC for SERDES PCB layouts
In order to be sure that SERDES bus traces on a routed printed circuit board are error free, you may use an automated design rule checker, which makes such tasks easier.
2004-11-17 Lattice upgrades PLD tool suite
The latest release of Lattice's ispLEVER features upgrades to the PLD design suite's performance and functionality
2002-09-12 Verisity creates component methodology manual
Verisity Inc. will launch a methodology manual and tutorial software to guide users through the process of creating testbench verification components that complies with the Specman Elite testbench generation tool
2011-03-15 Mentor enables signoff-quality verification during design
The Calibre RealTime platform gives designers access to Calibre's signoff engines and qualified decks during design, enhancing their layouts' performance without sacrificing manufacturing yield
2005-09-30 Synopsys testbench solution increases verification productivity
Synopsys announced Discovery Pioneer-NTB, a new SystemVerilog testbench automation tool that claims to increase verification productivity and improve the quality of complex SoC and IP designs
2006-02-17 Simplify partial reconfiguration for Xilinx's FPGAs
Xilinx announced the latest version of its PlanAhead software, which along with its ISE software, promises to deliver a two speed-grade performance advantage for Xilinx Virtex-4 and Spartan-3 FPGAs over competing offerings
2002-04-15 Researchers propose dual design verification model
Indian researchers are proposing a novel verification methodology that uses two representations of a design throughout the verification process, one a behavioral model in C and the other an RTL model
2006-04-20 EDA tool manages process variability early in design stage
Mentor Graphics announced its Calibre LFD (Litho-Friendly Design) product, which is touted to be the first production proven, EDA tool to address the urgent issue of how to manage process variability in the early stages of design creation
2013-06-27 Understanding deep packet inspection (Part 2)
Learn about several architectures and building blocks that ease the creation of scalable, reliable DPI
2004-12-10 Agere utilizes Verisity verification process automation
Agere Systems has used Verisity Ltd's verification process automation VPA products for a string of tape-outs including the ET1310 PCI Express Gigabit Ethernet controller.
2014-01-14 Accelerate M2M networking with UDP
Learn how user datagram protocol provides the simplest form of data transfer between network members.
2004-12-13 Synopsys, ARM partner on VIP suite for AMBA 3 AXI protocol
Synopsys disclosed that it has released the industry's first verification intellectual property suite for the AMBA 3 AXI protocol.
2001-06-01 Extraction method verifies IP functions
To keep in pace with silicon technology advancement, verification of the reused custom logic against its original counterpart should be considered as an integral part of the reuse process.
2014-04-08 Domain-specific languages for medical device design
Learn how existing languages for PLCs can be extended with domain-specific constructs.
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